參數(shù)資料
型號: STPCC0166BTI3
廠商: STMICROELECTRONICS
元件分類: 外設(shè)及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA388
封裝: PLASTIC, BGA-388
文件頁數(shù): 29/71頁
文件大?。?/td> 1238K
代理商: STPCC0166BTI3
Obsolete
Product(s)
- Obsolete
Product(s)
ELECTRICAL SPECIFICATIONS
Issue 2.4 - November 8, 2001
35/71
4.5.2 RESET sequence
Figure 4-4 describes the reset sequence of the
STPC, also called warm reset.
The constraints on the strap options and the bus
activities are the same as for the cold reset.
It is mandatory to have a clean reset pulse without
glitches as the STPC could then sample invalid
strap option setting and enter into an umpredicta-
ble mode.
While SYSRSTI# is active, the PCI clock PLL runs
in open loop mode at a speed of few 100’s KHz.
Figure 4-4. Reset timing diagram
S trap O ptions
SYSRSTI#
SYSRSTO #
14 M Hz
VA LID CONFIG URATIO N
HCLK
PCI_CLK
2.3 m s
IS AC LK
1.6 V
MD[63:0]
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