參數(shù)資料
型號： STPCC0166BTI3
廠商： STMICROELECTRONICS
元件分類： 外設(shè)及接口
英文描述： MULTIFUNCTION PERIPHERAL, PBGA388
封裝： PLASTIC, BGA-388
文件頁數(shù)： 35/71頁
文件大?。?/td> 1238K
代理商： STPCC0166BTI3
Obsolete
Product(s)
- Obsolete
Product(s)
ELECTRICAL SPECIFICATIONS
40/71
Issue 2.4 - November 8, 2001
Table 4-4. AC Memory Timing Characteristics
Parameter
Min
Max
Units
tCRAS
HCLK (or GCLK2X) to RAS#[3:0] valid (see Note 3)
17
ns
tCCAS
HCLK (or GCLK2X) to CAS#[7:0] bus valid (see Note 3)
17
ns
tCMA
HCLK (or GCLK2X) to MA[11:0] bus valid (see Note 3)
17
ns
tCMWE
HCLK (or GCLK2X) to MWE# valid (see Note 3)
17
ns
tCMD
HCLK to MD[63:0] bus valid (see Note 3)
25
ns
tGCMD
GCLK2X to MD[63:0] bus valid (see Note 3)
23
ns
tMDG
MD[63:0] Generic hold
0
ns
tCAH
Column Address Hold Time
≥1T
Cycles
ns
tCHR
CAS Hold Time
≥1T
Cycles
ns
tCOH
Data Hold TIme from CAS Low
Note 1
ns
tCPN
CAS Precharge Time
1TCycles
ns
tCRP
CAS to RAS Precharge Time
≤1T
Cycles
tCRW
CAS Low to RAS HIGH (Write only)
≥1T
Cycles
ns
tCSR
CAS Setup Time
≥1T
Cycles
ns
tDS
Data In Setup Time
≥1T
Cycles
ns
tRAH
Row Address Hold Time
≥1T
Cycles
ns
tRAS
RAS Pulse Width
≥3T
Cycles
ns
tRC
Random Read or Write Time Cycle
≥6T
Cycles
ns
tRCD
RAS to CAS Delay Time
≥1T
Cycles
ns
tRCH
Read Command Hold Time
≥1T
Cycles
ns
tRCS
Read Command Setup Time
≥1T
Cycles
ns
tRP
RAS Precharge Time
≥2T
Cycles
ns
tWCH
Write Command Hold Time
≥1T
Cycles
ns
tWCS
WE Command Setup Time
≥1T
Cycles
ns
tWRH
WE Hold Time
Note 2
ns
tWRP
WE Setup Time
≥1T
Cycles
ns
tAR
Column Address Hold Time from RAS
≥1T
Cycles
ns
tRAD
RAS to valid Column Address Delay
≥1T
Cycles
ns
tRAL
Column Address to RAS Setup Time
≥2T
Cycles
ns
tWCR
Write Command Hold Reference to RAS
≥1T
Cycles
ns
tRWL
Write Command to RAS Setup Time (Note 2)
≥1T
Cycles
ns
tCWL
Write Command to CAS Setup Time (Note 2)
≥1T
Cycles
ns
tDHR
Data Hold Reference to RAS
≥3T
Cycles
ns
tRPC
RAS High to CAS Low Precharge
≥1T
Cycles
ns
tCRS
CAS Before RAS Setup Time
≥1T
Cycles
ns
tCHR
CAS Before RAS Hold Time
≥1T
Cycles
ns
tCSH
CAS Hold Time after RAS
≥1T
Cycles
ns
Note 1; TCycle x nCAS + (tData off - tCAS out)
Where TCycle is the the number of clock cycles.
nCAS is the number of CAS Cycles (see section 6.7. )
TDataoff is the Generic Datahold
tCAS Out the CLK (either HCLK or GCLK2X) to CAS Low.
TDataoff and tCAS Out are used to refine the timing programming.
Note 2; Value to be derived from CAS pulse width which is programmable (see section 6.7. ).
Note 3; for all chronograms, CLK refers to the clock signal that the program is using. It can be either HCLK or GCLK2X
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