參數(shù)資料
型號: STP2200ABGA-100
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: 256M X 8, DRAM CONTROLLER, PBGA225
封裝: PLASTIC, BGA-225
文件頁數(shù): 7/36頁
文件大?。?/td> 433K
代理商: STP2200ABGA-100
15
Uniprocessor System Controller
USC
STP2200ABGA
July 1997
Figure 8 and Figure 9 show the best-case timing for non-cacheable single and block read from U2S referenced
to the time the P_Reply is issued from the slave. The timing for non-cacheable read from the fast frame buffer
(FFB) (UPA64S) is the same, except that it is referenced to a single-cycle P_RASB instead of the two-cycle
P_RAS/P_RAB.
Figure 8. Best-Case Timing for Noncached Single Read, UPA64 -> UPA128
Figure 9. Best-Case Timing for Noncached Block Read, UPA64 -> UPA128
Figure 10 and Figure 11 show the best-case timing for a non-cacheable single and block write to the U2S. A
non-cacheable write to the FFB has similar timing, except that the time it takes to forward the PRequest is
slightly less.
P_RAS
S_SRS
S_RAS
X_IPS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
UPA_PREPLY
UPA_SREPLY
to master
UPA_SREPLY
to slave
BMX_CMD
DATA_STALL
UPA_DATA 64
UPA_DATA 128
P_RAB
S_SRB
S_RBU
X_IPB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
UPA_PREPLY
UPA_SREPLY
to master
UPA_SREPLY
to slave
BMX_CMD
DATA_STALL
(CPU)
UPA_DATA 64
UPA_DATA 128
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