參數(shù)資料
型號(hào)： STP2200ABGA-100
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： 256M X 8, DRAM CONTROLLER, PBGA225
封裝： PLASTIC, BGA-225
文件頁(yè)數(shù)： 10/36頁(yè)
文件大小： 433K
代理商： STP2200ABGA-100
18
STP2200ABGA
Uniprocessor System Controller
USC
July 1997
Figure 16 and Figure 17 show the nominal timing for a U2S non-cacheable single and block read from the
processor.
Figure 16. Best-Case Timing for Noncached Single Read, UPA128 -> UPA64
Figure 17. Best-Case Timing for Noncached Block Read, UPA128 -> UPA64
Note:
Timing diagrams for U2S non-cacheable single and block write to the processor are not shown
because such transactions are dropped by the USC.
Figure 18 shows the “fast path” timing for memory reads issued from the processor. Fast paths are character-
ized by row address valid one cycle earlier than that of normal paths. The fast path is only available for reads
issued from the processor’s master class 0. It is not available for writes or for any accesses from the U2S. Nor-
mal paths are used for all transactions that are not processor reads from memory, for example, DMA, memory
writes, etc. See Figure 22 and Figure 23 for a graphic representation of fast paths and normal paths. Fast path
is not implemented for processor writes because for processor transaction type P_WRI_REQ (described in the
UPA specication) we need to examine the IVA bit (state bit embedded in the transaction packet, as described
in the UPA specication) before launching the request to memory, and the IVA bit is in the second half of the
PRequest packet. P_WRB_REQ (described in the UPA specication) almost always follows a victimizing read,
and this can be overlapped with the read. Accesses from the U2S are less latency sensitive. Since the fast path
is very timing critical and adds additional complexity to the logic, it is not implemented for the U2S.
S_RAS
X_PIS
P_RASB
S_SRS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
UPA_PREPLY
UPA_SREPLY
to master
UPA_SREPLY
to slave
BMX_CMD
DATA_STALL
UPA_DATA 64
UPA_DATA 128
S_RAB
X_PIB
P_RASB
S_SRB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
UPA_PREPLY
UPA_SREPLY
to master
UPA_SREPLY
to slave
BMX_CMD
DATA_STALL
UPA_DATA 64
UPA_DATA 128
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