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| 型號： | STP2200ABGA-100 |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | 256M X 8, DRAM CONTROLLER, PBGA225 |
| 封裝： | PLASTIC, BGA-225 |
| 文件頁數(shù)： | 34/36頁 |
| 文件大?。?/td> | 433K |
| 代理商： | STP2200ABGA-100 |
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7
Uniprocessor System Controller
USC
STP2200ABGA
July 1997
TECHNICAL OVERVIEW
The USC implements three UPA ports on two address buses. It has a programmable memory controller and
an EBus interface. Addresses ow through the USC. Data ows through the crossbar switches.
UPA Port Interface (PIF)
The PIF is responsible for receiving UPA packets, decoding their destinations, and forwarding the packets to
their proper destinations. The PIF also receives all P_Replys from UPA clients.
UPA address bus 0 has two clients: the processor and U2S (UPA-to-SBus Interface), or U2P (UPA-to-PCI Inter-
face). The PIF controls the arbitration on UPA address bus 0, for its two clients and itself. The two other
masters on this bus are the processor and one of the system I/O devices. The PIF arbitration algorithm is
described in the USC User Manual.
Noncached transactions are typically forwarded to a system I/O chip. Cached transactions are typically for-
warded to the memory controller. The PIF maintains data coherency in the system between the processor
cache, main memory, and the U2S merge buffer.
The UPA address bus 1 supports a single UPA64S device. This address bus is output only on the USC (for
example: unidirectional), and the USC is always the master. This interface is typically used for a graphic slave
device. The PIF will only generate and receive truncated P_Reply and S_Reply packets going to and coming
from the UPA64s device.
The PIF contains three sets of the following registers (one for each UPA port, processor, U2S, UPA 64S device):
SC_Port_Cong registers
SC_Port_Status registers
UPA Data Path Scheduler (DPS)
The DPS is responsible for regulating the ow of data throughout the system. It generates the following:
STP2230SOP (XB1/BMX) crossbar switch commands;
S_Replys for all clients;
UPA_DATA_STALL signals;
UPA_ECC_VAL signals.
DPS contains no software-visible registers.
Memory Controller (MC)
The MC is responsible for controlling the SIMMs. It performs the following functions:
Generates timing for read, write, and refresh;
Converts the physical address in the UPA packet into row and column addresses;
Maintains the refresh timer;
Controls loading and unloading of data from the XB1 read and write buffers.
The PIF forwards memory requests to the MC. The MC communicates with the DPS to schedule delivery of
data.
The MC contains the following registers:
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STP2200ABGA-83 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System Controller |
| STP2202ABGA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System Controller |
| STP2205BGA | 制造商:SUN 功能描述: |
| STP220N6F7 | 功能描述:MOSFET N-CH 60V 120A TO-220 制造商:stmicroelectronics 系列:STripFET? F7 包裝:管件 零件狀態(tài):有效 FET 類型:MOSFET N 通道，金屬氧化物 FET 功能:標(biāo)準(zhǔn) 漏源極電壓（Vdss）:60V 電流 - 連續(xù)漏極（Id）（25°C 時）:120A（Tc） 不同?Id，Vgs 時的?Rds On（最大值）:2 毫歐 @ 60A，10V 不同 Id 時的 Vgs（th）（最大值）:4V @ 250μA 不同 Vgs 時的柵極電荷（Qg）:100nC @ 10V 不同 Vds 時的輸入電容（Ciss）:6400pF @ 25V 功率 - 最大值:237W 工作溫度:-55°C ~ 175°C（TJ） 安裝類型:通孔 封裝/外殼:TO-220-3 供應(yīng)商器件封裝:TO-220 標(biāo)準(zhǔn)包裝:50 |
| STP2210QFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interrupt Controller |
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