參數(shù)資料
型號: STP2200ABGA-100
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: 256M X 8, DRAM CONTROLLER, PBGA225
封裝: PLASTIC, BGA-225
文件頁數(shù): 35/36頁
文件大小: 433K
代理商: STP2200ABGA-100
8
STP2200ABGA
Uniprocessor System Controller
USC
July 1997
MC_Control 0; and
MC_Control 1
These registers are described in further detail in the USC User Guide.
EBus Interface (EB)
The EB implements an interface to EBus, an asynchronous 8-bit interface controlled by the STP2001 Slave I/O
Controller (SLAVIO). Since the USC contains no UPA data path, all reading and writing of internal registers
has to take place via EBus. Since all internal registers are 32 bits wide, the EB has to perform packing and
unpacking.
The EB block implements reset logic and contains a number of global registers.
SC_Control register for controlling resets and logging reset status;
SC_ID register, which contains the USC’s JEDEC ID number, implementation and version numbers, and
the number of UPA ports that the chip supports;
Performance counters: SC_Perf_Ctrl, SC_Perf0, and SC_Perf1. These counters can be congured to count
various events for performance analysis.
Clock and PLL
The USC will operate at a maximum frequency of 100 MHz (10 nanoseconds cycle time). It is a completely
synchronous, edge-triggered, register-based design which uses only the rising edge of the clock to update the
ip-ops.
The chip also contains a phase-locked loop (PLL) to remove the skew introduced by the internal clock distri-
bution network. This improves I/O timing.
JTAG Interface
The USC provides a JTAG interface for full chip scan which is used only for ATPG and in-system interconnect
testing. The USC’s boundary is shadowed to allow for board-level test.
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