參數(shù)資料
型號: STP2200ABGA-100
元件分類: 存儲控制器/管理單元
英文描述: 256M X 8, DRAM CONTROLLER, PBGA225
封裝: PLASTIC, BGA-225
文件頁數(shù): 31/36頁
文件大小: 433K
代理商: STP2200ABGA-100
4
STP2200ABGA
Uniprocessor System Controller
USC
July 1997
SIGNAL DESCRIPTIONS
UPA Interface Signals
Signal
I/O
Description
UPA_ADDRBUS0[34:0]
I/O
Address bus 0 (processor/U2S)
UPA_ADR0_PAR
I/O
Parity for address bus 0
UPA_ADDR0_VAL[1:0]
I/O
[0] = processor, [1] = U2S
UPA_SC_REQ0
O
USC request for address bus 0
UPA_REQIN0[1:0]
I
Client address bus 0 arbitration requests: [0] = processor, [1] = U2S
UPA_ADDRBUS1[28:0]
O
Address bus for UPA64S
UPA_ADDR1_VAL1
O
Address valid signal for UPA64S
UPA_SREPLY0_[4:0]
O
S_Reply for processor
UPA_SREPLY1_[4:0]
O
S_Reply for U2S
UPA_SREPLY2_[2:0]
O
S_Reply for UPA64S
UPA_PREPLY0_[4:0]
I
P_Reply from processor
UPA_PREPLY1_[4:0]
I
P_Reply from U2S
UPA_PREPLY2_[1:0]
I
P_Reply from UPA64S
UPA_RESET0
O
Reset for processor, tied to the U2S’s UPA_ARB_RESET
UPA_RESET1
O
Reset for U2S
UPA_XIR
O
XIR reset for processor only
UPA_ECC_VAL_0
O
ECC valid for processor
UPA_ECC_VAL_1
O
ECC valid for U2S
UPA_DATA_STALL0
O
Stall data to processor
UPA_DATA_STALL1
O
Stall data to U2S
Memory Interface Signals
Signal
I/O
Description
MEMADDR[12:0]
O
Row/column address
RAS[3:0]
O
RAS per SIMM pair
CAS[3:0]
O
CAS (four copies)
WE
O
Write enable
Crossbar Interface Signals
Signal
Type
Description
BMX_CMD0[3:0]
O
Command to XB1 crossbar array of 18 devices
MRB_CTRL0
O
Fill the XB1 read buffer
MWB_CTRL0
O
Drain the XB1 write buffer
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