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參數(shù)資料
| 型號(hào)： | STE2004S |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | M16C; M16C/60 Series; Microcontroller; Bit Size: 32/16-bit CISC; ROM: 320K; RAM: 31K; ROM Type: Mask ROM; CPU: M16C/60 core; Minimum Instruction Execution Time (ns): 41.7 (@24MHz); Operating Frequency / Supply Voltage: 24MHz/3.0 to 5.5V, 10MHz/2.7 to 5.5V; Operating Ambient Temperature (°C): -20 to 85, -40 to 85; Package Code: PLQP0128KB-A (128P6Q-A) |
| 中文描述： | 102 × 65的單芯片LCD控制器/驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 67/79頁(yè) |
| 文件大?。?/td> | 1123K |
| 代理商： | STE2004S |
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STE2004S
Electrical characteristics
67/79
7.3
AC operation
VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15
V; Tamb =25°C;
unless otherwise specified.
Table 28. AC operation
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Internal oscillator (
Figure 71
)
F
OSC
Internal oscillator
frequency
V
DD
= 2.8V
61
72
83
kHz
F
EXT
External oscillator
frequency
20
100
kHz
F
FRAME
Frame frequency
fosc or fext = 72 kHz
(1)
75
Hz
T
w(RES)
RES LOW pulse width
5
μ
s
Reset pulse rejection
1
μ
s
T
LOGIC
(RES)
Internal logic reset time
5
μ
s
T
VDD
VDD1 vs. VDD2 Delay
0
μ
s
I
2
C bus interface (
Figure 72
)
(2)
(3)
F
SCL
SCL clock frequency
Fast mode
DC
400
kHz
High speed mode;
Cb=100pF (max);
(4)
V
DD1
=2
DC
3.4
MHz
High speed mode;
Cb=400pF (max)
(4)
;
V
DD1
=2
Fast Mode
(4)
;V
DD1
=1.7V
DC
1.7
MHz
400
KHz
T
SU;STA
Set-up time (repeated)
START condition
Cb = 100pF
(5)
(6)
160
ns
T
HD;STA
Hold time (repeated)
START condition
Cb = 100pF
(5)
(6)
160
ns
T
LOW
Low period of SCLH
clock
Cb = 100pF
(5)
(6)
160
ns
T
HIGH
High period of SCLH
clock
Cb = 100pF
(5)
(6)
160
ns
T
SU;DAT
Data set-up time
Cb = 100pF
(5)
(6)
60
ns
T
HD;DAT
Data hold time
Cb = 100pF
(5)
(6)
10
ns
T
r;CL
Rise time of SCLH signal Cb = 100pF
(5)
(6)
10
ns
T
r;CL1
Rise time of SCLH signal
after a repeated START
condition and aftyer an
acknowledge bit
Cb = 100pF
(5)
(6)
10
ns
T
f;CL
Fall time of SCLH signal
Cb = 100pF
(5)
(6)
10
ns
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