參數(shù)資料
型號(hào)： STE2004S
廠商： 意法半導(dǎo)體
英文描述： M16C; M16C/60 Series; Microcontroller; Bit Size: 32/16-bit CISC; ROM: 320K; RAM: 31K; ROM Type: Mask ROM; CPU: M16C/60 core; Minimum Instruction Execution Time (ns): 41.7 (@24MHz); Operating Frequency / Supply Voltage: 24MHz/3.0 to 5.5V, 10MHz/2.7 to 5.5V; Operating Ambient Temperature (°C): -20 to 85, -40 to 85; Package Code: PLQP0128KB-A (128P6Q-A)
中文描述： 102 × 65的單芯片LCD控制器/驅(qū)動(dòng)器
文件頁數(shù)： 31/79頁
文件大?。?/td> 1123K
代理商： STE2004S
STE2004S
Bus interfaces
31/79
4
Bus interfaces
To provide the widest flexibility and ease of use the STE2004S features six different
methods for interfacing the host controller. To select the desired interface the SEL1, SEL2
and SEL3 pads need to be connected to a logic LOW (connect to GND) or a logic HIGH
(connect to VDD). All the I/O pins of the unused interfaces must be connected to GND.
All interfaces work while the STE2004S is in power down.
Table 7. Bus interfaces
4.1
I
2
C Interface
The I
2
C interface is a fully complying I
2
C bus specification, selectable to work in both Fast
(400kHz Clock) and High Speed Mode (3.4MHz).
This bus is intended for communication between different LCs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL
lines must be connected to a positive supply voltage via an active or passive pull-up.
The following protocol has been defined:
–
Data transfer may be initiated only when the bus is not busy.
–
During data transfer, the data line must remain stable whenever the clock line is
high. Changes in the data line while the clock line is high are interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
BUS not busy:
Both data and clock lines remain High.
Start Data Transfer:
A change in the state of the data line, from High to Low, while the clock
is High, define the START condition.
Stop Data Transfer:
A Change in the state of the data line, from low to High, while the clock
signal is High, defines the STOP condition.
Data Valid:
The state of the data line represents valid data when after a start condition, the
data line is stable for the duration of the High period of the clock signal. The data on the line
may be changed during the Low period of the clock signal. There is one clock pulse per bit
of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and the stop conditions is not
SEL3
SEL2
SEL1
Interface
Note
0
0
0
I
2
C
Read and write; fast and
high speed mode
0
0
1
SPI 4 lines 8 bit
Read and write
0
1
0
SPI 3 lines 8 bit
Read and write
0
1
1
Serial 3 lines 9 bit
Read and write
1
0
0
Parallel 8080-series
Read and write
1
0
1
Parallel 68000-series
Read and write
相關(guān)PDF資料
PDF描述
STE2004SDIE2 102 x 65 single-chip LCD controller/driver
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
STE2004SDIE2 制造商:STMicroelectronics 功能描述:
STE2007 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:96 x 68 Single-chip LCD controller/driver
STE2007_06 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:96 x 68 Single-chip LCD controller/driver
STE2007DIE2 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:96 x 68 Single-chip LCD controller/driver
STE200GRL 制造商:Thomas & Betts 功能描述:Fittings Locknut 2inch Female
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