參數(shù)資料
型號(hào): STE2004SDIE2
廠商: 意法半導(dǎo)體
英文描述: 102 x 65 single-chip LCD controller/driver
中文描述: 102 × 65的單芯片LCD控制器/驅(qū)動(dòng)器
文件頁(yè)數(shù): 1/79頁(yè)
文件大?。?/td> 1123K
代理商: STE2004SDIE2
January 2007
Rev 3
1/7979
79
STE2004S
102 x 65 single-chip LCD controller/driver
Features
102 x 65 bits display data RAM
Programmable MUX rate
Programmable frame rate
X,Y programmable carriage return
Dual partial display mode
Row by row scrolling
N-line inversion
Automatic data RAM blanking procedure
Selectable input interface:
– I
2
C Bus Fast and Hs-mode (read and write)
– 8000 and 8080 Parallel Interfaces (read
and write)
– 3-lines and 4-lines SPI Interface (read and
write)
– 3-lines 9 bit Serial Interface (read and
write)
Fully integrated configurable LCD bias voltage
generator with:
– Selectable
multiplication factor (up to
5
X
)
– Effective sensing for high precision output
– Eight selectable temperature compensation
coefficients
CMOS compatible inputs
Fully integrated oscillator requires no external
components
Designed for chip-on-glass (COG)
applications.
Low power consumption, suitable for battery
operated systems
Logic supply voltage range from 1.7 to 3.6V
High voltage generator supply voltage range
from 1.75 to 4.5V
Display supply voltage range from 4.5 to 14.5V
Backward compatibility with STE2001/2/4
Description
The STE2004S is a low power CMOS LCD
controller driver. Designed to drive a 65 rows by
102 columns graphic display, it provides all
necessary functions in a single chip, including
on-chip LCD supply and bias voltages generators,
resulting in a minimum of externals components
and in a very low power consumption.
STE2004S features six standard interfaces
(3-lines Serial, 3-lines SPI, 4-lines SPI, 68000
Parallel, 8080 parallel and I
2
C) for interfacing with
the host micro-controller.
COLUMN
DRIVERS
ROW
DRIVERS
DATA
LATCHES
65 x 102
RAM
DISPLAY
CONTROL
LOGIC
SCROLL
LOGIC
DATA
REGISTER
INSTRUCTION
REGISTER
CO to C101
R0 to R64
VSENSE SLAVE
RES
VDD1,2
CLOCK
TIMING
GENERATOR
BIAS VOLTAGE
GENERATOR
HIGH VOLTAGE
GENERATOR
RESET
TEST
SHIFT
REGISTER
VLCD
V
SS
EXT
ICON_MODE
VSSAUX
SAO
SDIN/SDA_IN SDA_OUT
SCLK/SCL
DB0
to
DB7
9 Bit SERIAL
D/C
CS
SA1
SDOUT
E/WR R/W- RD
I2C BUS
3 & 4 Line SPI
Parallel 8080
Parallel 68K
SEL 3
SEL 2
SEL 1
TEST_VREF
TEST_MODE
LR0047
OSC
OSC_IN
OSC_OUT
FR_IN
FR_OUT
MASTER
SLAVE SYNC
VLCDSENSE
www.st.com
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