- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380763 > STE2004SDIE2 (意法半導(dǎo)體) 102 x 65 single-chip LCD controller/driver PDF資料下載
參數(shù)資料
| 型號： | STE2004SDIE2 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 102 x 65 single-chip LCD controller/driver |
| 中文描述： | 102 × 65的單芯片LCD控制器/驅(qū)動器 |
| 文件頁數(shù)： | 14/79頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | STE2004SDIE2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁
Circuit description
STE2004S
14/79
3.8
Display data RAM
The STE2004S, provides an 102X65 bits static RAM to store display data. This is organized
into 9 (Bank0 to Bank8) banks with 102 bytes. One of these banks can be used for icons.
RAM access is accomplished in either one of the bus interfaces provided (see below).
Allowed addresses are X0 to X101 (Horizontal) and Y0 to Y8 (Vertical).
There are four address mode provided to write to RAM:
Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on
the left of the memory map. The X pointer is increased after each byte written. After the
last column address (X=X-Carriage), Y address pointer jumps to the following bank and
X restarts from X=0. (
Figure 8.
)
Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the
left of the memory map. The Y pointer is increased after each byte written. After the last
Y bank address (Y=Y-Carriage), X address pointer jumps to next column and Y restarts
from Y=0 (
Figure 9
).
Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on
the right of the memory map. The X pointer is increased after each byte written. After
the last column address (X=X-Carriage), Y address pointer jumps to the next bank and
X restarts from X=0 (
Figure 10.
).
Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the
right of the memory map. The Y pointer is increased after each byte written. After the
last Y bank address (Y=Y-Carriage), the X pointer jumps to next column and Y restarts
from Y=0 (
Figure 11.
).
●
●
●
●
After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always
jumps to the cell with address (X;Y) = (0;0) (
Figure 12.
Figure 13.
Figure 14.
Figure 15.
).
Data bytes in the memory could have the MSB either on top (D0 = 0,
Figure 16.
) or on the
bottom (D0=1,
Figure 17.
).
The STE2004S also allows the normal output address to be altered. The display is mirrored
along the X axis if a logic one MY bit is set. Only the memory read process is altered, the
content is not affected in memory.
When
ICON MODE=1
the icon row is not mirrored with MY and is not scrolled.
When
ICON MODE=0
the icon row is like an other graphic line and is mirrored and scrolled.
When the partial display mode is disabled, there are three multiplex ratios available (MUX
33, MUX 49 and MUX 65). Only a subset of writable rows are output on row drivers in MUX
33,49 and 65 modes.
When
Y-Carriage<MUX/8
, if MUX 49 is selected only the first 49 memory rows are
visualized; if MUX 33 selected, only the first 33 memory rows. The unused output row and
column drivers must be left floating.
When
Y-Carriage<=MUX/8
the icon bank is located to BANK 8 in MUX 65 Mode, to BANK6
in MUX 49 Mode, and to BANK 4 in MUX 33 Mode.
In MUX 33 and MUX 49 modes and
Y-Carriage>MUX/8
, only lines 33 and 49 are
visualized.
The lines of DDRAM connected on the output drivers using the scrolling function (Range: 0-
Y-Carriage*8) are selectable. When
Y-Carriage>MUX/8
lines, the icon row is moved in
DDRAM to the first row of the bank, corresponding to the Y-CARRIAGE Return value, being
always connected on the same output Driver.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STE2130S | 240RGB x 320 single chip true 262K color controller/driver |
| STE26NA90 | N-Channel 900V-0.25Ω-26A-ISOTOP Fast Power MOSFET(N溝道快速功率MOSFET) |
| STE36N50 | N-CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR IN ISOTOP PACKAGE |
| STE38NB50 | N-Channel 500V-0.11Ω-38A- ISOTOP PowerMESHTM MOSFET(N溝道MOSFET) |
| STE40NK90ZD | N-CHANNEL 900V - 0.14 - 40 A ISOTOP Super FREDMeshTM MOSFET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STE2007 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:96 x 68 Single-chip LCD controller/driver |
| STE2007_06 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:96 x 68 Single-chip LCD controller/driver |
| STE2007DIE2 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:96 x 68 Single-chip LCD controller/driver |
| STE200GRL | 制造商:Thomas & Betts 功能描述:Fittings Locknut 2inch Female |
| STE200S | 制造商:Thomas & Betts 功能描述:-200S |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。