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參數(shù)資料
| 型號： | STE2004SDIE2 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 102 x 65 single-chip LCD controller/driver |
| 中文描述： | 102 × 65的單芯片LCD控制器/驅(qū)動器 |
| 文件頁數(shù)： | 36/79頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | STE2004SDIE2 |
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Bus interfaces
STE2004S
36/79
Figure 37.
4-lines SPI reading sequence
4.2.2
3-lines SPI interface
The STE2004S 3-lines serial interface is a bidirectional link between the display driver and
the application supervisor.
It consists of three lines: one/two for data signals (SDIN,SDOUT), one for clock signals
(SCLK) and one for peripheral enable (CS).
If the R/W bit is set to logic 0 the STE2004S is set to be a receiver. One or more command
words follow to define the status of the device.
A command word is composed by two bytes. The first is a control byte which defines Co,
D/C, R/W H[1;0] and HE values, the second is a data byte (
Figure 38.
). The Co bit is the
command MSB and defines whether the command is followed by one data byte and an
other command word, or if it is followed by a stream of commands, or a steam of DDRAM
data (Co = 1 Command word, Co = 0 Stream of data). The D/C bit defines whether the data
byte is a command or DDRAM data (D/C = 1 RAM Data, D/C = 0 Command). The H[1;0] bits
define the instruction Set Page if HE bit =1. If HE bit is set to 0, H[1;0] values are neglected
and it is possible to update the instruction set page number using only the related instruction
in the instruction set.
If Co =1 and D/C = 0, the incoming data byte is decoded as a command, and if Co =1 and
D/C =1, the following data byte is stored in the data RAM at the location specified by the
data pointer.
After the last control byte, if D/C is set to a logic 1, the incoming data bytes are stored inside
the STE2004S display data RAM starting at the address specified by the data pointer. The
data pointer is automatically updated after every byte written and in the end points to the last
RAM location written.
READING SEQUENCE
Write a "00000000" Instruction
Source 8 pulses on SCLK and
Read the ID Number or the Status Byte On SDOUT
END OF READING SEQUENCE
SDOUT Buffer Configured in High Impedence
LR0078
SDOUT Buffer becomes active (Low Impedence)
1
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read
.
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相關(guān)代理商/技術(shù)參數(shù) |
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