參數(shù)資料
型號(hào): SJA1000
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Stand-alone CAN controller(單機(jī)CAN控制器)
中文描述: 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁(yè)數(shù): 50/68頁(yè)
文件大?。?/td> 234K
代理商: SJA1000
2000 Jan 04
50
Philips Semiconductors
Product specification
Stand-alone CAN controller
SJA1000
6.5
Common registers
6.5.1
B
US
T
IMING
R
EGISTER
0 (BTR0)
The contents of the bus timing register 0 defines the values of the Baud Rate Prescaler (BRP) and the Synchronization
Jump Width (SJW). This register can be accessed (read/write) if the reset mode is active.
In operating mode this register is read only, if the PeliCAN mode is selected. In BasicCAN mode a ‘FFH’ is reflected.
Table 44
Bit interpretation of bus timing register 0 (BTR0); CAN address 6
6.5.1.1
Baud Rate Prescaler (BRP)
The period of the CAN system clock t
scl
is programmable and determines the individual bit timing. The CAN system clock
is calculated using the following equation:
t
scl
= 2
×
t
CLK
×
(32
×
BRP.5 + 16
×
BRP.4 + 8
×
BRP.3 + 4
×
BRP.2 + 2
×
BRP.1 + BRP.0 + 1)
where t
CLK
= time period of the XTAL frequency =
6.5.1.2
Synchronization Jump Width (SJW)
To compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must
re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the
maximum number of clock cycles a bit period may be shortened or lengthened by one re-synchronization:
t
SJW
= t
scl
×
(2
×
SJW.1 + SJW.0 + 1)
6.5.2
B
US
T
IMING
R
EGISTER
1 (BTR1)
The contents of bus timing register 1 defines the length of the bit period, the location of the sample point and the number
of samples to be taken at each sample point. This register can be accessed (read/write) if the reset mode is active.
In operating mode, this register is read only, if the PeliCAN mode is selected. In BasicCAN mode a ‘FFH’ is reflected.
Table 45
Bit interpretation of bus timing register 1 (BTR1); CAN address 7
6.5.2.1
Sampling (SAM)
BIT 7
SJW.1
BIT 6
SJW.0
BIT 5
BRP.5
BIT 4
BRP.4
BIT 3
BRP.3
BIT 2
BRP.2
BIT 1
BRP.1
BIT 0
BRP.0
BIT 7
SAM
BIT 6
TSEG2.2
BIT 5
TSEG2.1
BIT 4
TSEG2.0
BIT 3
TSEG1.3
BIT 2
TSEG1.2
BIT 1
TSEG1.1
BIT 0
TSEG1.0
BIT
VALUE
FUNCTION
SAM
1
triple; the bus is sampled three times; recommended for low/medium speed buses
(class A and B) where filtering spikes on the bus line is beneficial
single; the bus is sampled once; recommended for high speed buses (SAE class C)
0
XTAL
f
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