參數(shù)資料
型號: SJA1000
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Stand-alone CAN controller(單機CAN控制器)
中文描述: 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁數(shù): 14/68頁
文件大小: 234K
代理商: SJA1000
2000 Jan 04
14
Philips Semiconductors
Product specification
Stand-alone CAN controller
SJA1000
Table 4
Bit interpretation of the command register (CMR); CAN address 1
Notes
1.
The SJA1000 will enter sleep mode if the sleep bit is set to logic 1 (sleep); there is no bus activity and no interrupt is
pending. Setting of GTS with at least one of the previously mentioned exceptions valid will result in a wake-up
interrupt. After sleep mode is set, the CLKOUT signal continues until at least 15 bit times have passed, to allow a
host microcontroller clocked via this signal to enter its own standby mode before the CLKOUT goes LOW.
The SJA1000 will wake up when one of the three previously mentioned conditions is negated: after ‘Go To Sleep’ is
set LOW (wake-up), there is bus activity or INT is driven LOW (active). On wake-up, the oscillator is started and a
wake-up interrupt is generated. A sleeping SJA1000 which wakes up due to bus activity will not be able to receive
thismessageuntilitdetects11 consecutiverecessivebits(bus-freesequence).ItshouldbenotedthatsettingofGTS
isnotpossible inreset mode.Afterclearingofreset request,settingofGTSispossiblefirst, whenbus-freeisdetected
again.
This command bit is used to clear the data overrun condition indicated by the data overrun status bit. As long as the
data overrun status bit is set no further data overrun interrupt is generated. It is allowed to give the clear data overrun
command at the same time as a release receive buffer command.
After reading the contents of the receive buffer, the microcontroller can release this memory space of the RXFIFO
by setting the release receive buffer bit to logic 1. This may result in another message becoming immediately
available within the receive buffer. This event will force another receive interrupt, if enabled. If there is no other
message available no further receive interrupt is generated and the receive buffer status bit is cleared.
The abort transmission bit is used when the CPU requires the suspension of the previously requested transmission,
e.g. to transmit a more urgent message before. A transmission already in progress is not stopped. In order to see if
the original message had been either transmitted successfully or aborted, the transmission complete status bit
should be checked. This should be done after the transmit buffer status bit has been set to logic 1 (released) or a
transmit interrupt has been generated.
If the transmission request was set to logic 1 in a previous command, it cannot be cancelled by setting the
transmission request bit to logic 0. The requested transmission may be cancelled by setting the abort transmission
bit to logic 1.
2.
3.
4.
5.
BIT
SYMBOL
GTS
NAME
VALUE
1
FUNCTION
CMR.7
CMR.6
CMR.5
CMR.4
Go To Sleep; note 1
reserved
reserved
reserved
sleep; the SJA1000 enters sleep mode if no CAN
interrupt is pending and there is no bus activity
wake up; SJA1000 operates normal
clear; data overrun status bit is cleared
no action
released; the receive buffer, representing the
message memory space in the RXFIFO is
released
no action
present; if not already in progress, a pending
transmission request is cancelled
absent; no action
present; a message will be transmitted
absent; no action
0
1
0
1
CMR.3
CDO
Clear Data Overrun;
note 2
CMR.2
RRB
Release Receive Buffer;
note 3
0
1
CMR.1
AT
Abort Transmission;
note 4
0
1
0
CMR.0
TR
Transmission Request;
note 5
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