參數(shù)資料
型號: SJA1000
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Stand-alone CAN controller(單機CAN控制器)
中文描述: 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁數(shù): 44/68頁
文件大?。?/td> 234K
代理商: SJA1000
2000 Jan 04
44
Philips Semiconductors
Product specification
Stand-alone CAN controller
SJA1000
Table 41
RX identifier 4 (EFF); can address 20; note 1
Notes
1.
2.
ID.X means identifier bit X.
Remote transmission request.
BIT 7
ID.4
BIT 6
ID.3
BIT 5
ID.2
BIT 4
ID.1
BIT 3
ID.0
BIT 2
RTR
(2)
BIT 1
0
BIT 0
0
Remark:
the received data length code located in the
frameinformationbyterepresentstherealsentdatalength
code, which may be greater than 8 (depends on sender).
Nevertheless the maximum number of received data bytes
is 8. This should be taken into account by reading a
message from the receive buffer.
As described in Fig.8 the RXFIFO has space for
64 message bytes in total. It depends on the data length
how many messages can fit in it at one time. If there is not
enough space for a new message within the RXFIFO, the
CAN controller generates a data overrun condition the
moment this message becomes valid and the acceptance
test was positive. A message which is partly written into
the RXFIFO, when the data overrun situation occurs, is
deleted. This situation is indicated to the CPU via the
status register and the data overrun interrupt, if enabled.
6.4.15
A
CCEPTANCE FILTER
With the help of the acceptance filter the CAN controller is
abletoallow passingof receivedmessages to theRXFIFO
only when the identifier bits of the received message are
equal to the predefined ones within the acceptance filter
registers.
The acceptance filter is defined by the Acceptance Code
Registers (ACRn) and the Acceptance Mask Registers
(AMRn). The bit patterns of messages to be received are
defined within the acceptance code registers.
The corresponding acceptance mask registers allow to
define certain bit positions to be ‘don’t care’.
Two different filter modes are selectable within the mode
register (MOD.3, AFM; see Section 6.4.3):
Single filter mode (bit AFM is logic 1)
Dual filter mode (bit AFM is logic 0).
6.4.15.1
Single filter configuration
In this filter configuration one long filter (4-bytes) could be
defined. The bit correspondences between the filter bytes
and the message bytes depend on the currently received
frame format.
Standard frame:
if a standard frame format message is
received, the complete identifier including the RTR bit and
the first two data bytes are used for acceptance filtering.
Messages may also be accepted if there are no data bytes
existing due to a set RTR bit or if there is none or only one
data byte because of the corresponding data length code.
For a successful reception of a message, all single bit
comparisons have to signal acceptance.
Note, that the 4 least significant bits of AMR1 and ACR1
arenotused.Inordertobecompatiblewithfutureproducts
these bits should be programmed to be ‘don’t care’ by
setting AMR1.3, AMR1.2, AMR1.1 and AMR1.0 to logic 1.
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