
C165H
System Control Unit (CSCU)
Data Sheet
429
2001-04-19
PRELMNARY
GRPDIS
Peripheral Group Disable Flag (PD-Bus and X-Bus Peripherals)
‘
0
’
: Peripheral clock driver for peripheral group is enabled
‘
1
’
: Peripheral clock driver for peripheral group is disabled
-EXCERPT-
PLL Disable Flag (additional power savings / noise reduction feature)
‘
0
’
: The PLL of the C165H is switched on. This is the
default
configuration.
‘
1
’
: The PLL is completely switched off. The free running feature and the
oscillator watchdog will not work, since there is no PLL clock at all.
Note:
It makes sense to switch off the PLL in
direct drive
clock mode only.
19.5
Peripheral Management Module
This module especially serves for power management support, controlling dynamically
the operation and thus the power consumption of the different peripherals on PD Bus
and XBUS.
In each situation (eg. several system operating modes, standby, etc.) only
those peripherals may be kept running which are required for the respective functionality.
peripherals.
Peripheral’s operation is disabled or enabled by controlling the specific clock input. This
function also is supported in idle and/or slow down mode.
The Real Time Clock (RTC) may be fed by a separate clock driver, so it can be kept
running even in power down mode.
While a peripheral is disabled its output pins remain in the state they had at the time of
disabling.
Note:
In contrast to the peripheral management of Infineon’s 16x family the registers of
a
disabled
module are not accessable. Only the clock control register of the
platform peripheral is accessable. Note, the register access is not compatible to
the C167CS.
The user gets access to the flexible operation control of peripherals via the SYSCON3
register. This register is defined as follows:
SYSCON3 (F1D4
H
/ EA
H
)
15
14
GRP
DIS
serv
ed
ESFR-b
Reset Value:0000
H
2
1
PER
DIS1
DIS2
.
Bit
Function
PERDISx
Peripheral Disable Flag 0 - 14
‘
0
’
: Module is enabled; the peripheral is supplied with the clock signal
‘
1
’
: Module is disabled; the clock input of peripheral is disabled
PLLDIS
5
4
3
0
11
10
9
8
7
6
13
PLL
DIS
12
-
-
rw
rw
-
rw
rw
rw
rw
rw
PER
DIS0
-
rw
rw
rw
PER
PER
DIS3
reserved
PER
DIS6
PER
DIS7
PER
DIS8
reserved
-
re-
reserved