
C165H
External Bus Interface
Data Sheet
175
2001-04-19
PRELMNARY
9.2
Programmable Bus Characteristics
-EXCERPT-
Important timing characteristics of the external bus interface have been made user
programmable to allow to adapt it to a wide range of different external bus and memory
configurations with different types of memories and/or peripherals.
The following parameters of an external bus cycle are programmable:
Read or Write Chip Select
signals remain active only as long as the associated control
signal (RD or WR) is active. This also includes the programmable read/write delay. Read
chip select is only activated for read cycles, write chip select is only activated for write
cycles, read/write chip select is activated for both read and write cycles (write cycles are
assumed, if any of the signals WRH or WRL gets active). These modes save external
glue logic, when accessing external devices like latches or drivers that only provide a
single enable input.
Note:
CS0 provides an address chip select directly after reset (except for single chip
mode) when the first instruction is fetched.
Internal pullup devices hold all CS lines high during reset. After the end of a reset
sequence the pullup devices are switched off and the pin drivers control the pin levels
on the selected CS lines. Not selected CS lines will enter the high-impedance state and
are available for general purpose I/O.
The pullup devices are also active during bus hold on the selected CS lines, while HLDA
is active and the respective pin is switched to push/pull mode. Open drain outputs will
float during bus hold. In this case external pullup devices are required or the new bus
master is responsible for driving appropriate levels on the CS lines.
Segment Address versus Chip Select
The external bus interface of the C165H supports many configurations for the external
memory. By increasing the number of segment address lines the C165H can address a
linear address space of 256 KByte, 1 MByte or 8 MByte. This allows to implement a large
sequential memory area, and also allows to access a great number of external devices,
using an external decoder. By increasing the number of CS lines the C165H can access
memory banks or peripherals without external glue logic. These two features may be
combined to optimize the overall system performance. Enabling 4 segment address lines
and 5 chip select lines eg. allows to access five memory banks of 8 MByte each. So the
available address space is 40 MByte (without glue logic).
Note:
Bit SGTDIS of register SYSCON defines, if the CSP register is saved during
interrupt entry (segmentation active) or not (segmentation disabled).
ALE Control
defines the ALE signal length and the address hold time after its falling edge
Memory Cycle Time
(extendable with 1...15 waitstates) defines the allowable access time
Memory Tri-State Time
(extendable with 1 waitstate) defines the time for a data driver to float