
C165H
Interrupt and Trap Functions
Data Sheet
110
2001-04-19
PRELMNARY
response time under these conditions is 6 state times (12 TCL).
The interrupt response time is increased by all delays of the instructions in the pipeline
that are executed before entering the service routine (including N).
When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, or
instruction N explicitly writes to the PSW or the SP, the minimum interrupt response
time may be extended by 1 state time for each of these conditions.
When instruction N reads an operand from the internal code memory, or when N is a
call, return, trap, or MOV Rn, [Rm+ #data16] instruction, the minimum interrupt
-EXCERPT-
Figure 23
Pipeline Diagram for Interrupt Response Time
All instructions in the pipeline including instruction N (during which the interrupt request
flag is set) are completed before entering the service routine. The actual execution time
for these instructions (eg. waitstates) therefore influences the interrupt response time.
In the figure above the respective interrupt request flag is set in cycle 1 (fetching of
instruction N). The indicated source wins the prioritization round (during cycle 2). In cycle
3 a TRAP instruction is injected into the decode stage of the pipeline, replacing
instruction N+1 and clearing the source's interrupt request flag to '0'. Cycle 4 completes
the injected TRAP instruction (save PSW, IP and CSP, if segmented mode) and fetches
the first instruction (I1) from the respective vector location.
All instructions that entered the pipeline after setting of the interrupt request flag (N+1,
N+2) will be executed after returning from the interrupt service routine.
The minimum interrupt response time is 5 states (10 TCL). This requires program
execution from the internal code memory, no external operand read requests and setting
the interrupt request flag during the last state of an instruction cycle. When the interrupt
request flag is set during the first state of an instruction cycle, the minimum interrupt
Pipeline Stage
Cycle 1
Cycle 2
Cycle 3
Cycle 4
FETCH
N
N + 1
N + 2
I1
DECODE
N - 1
N
TRAP (1)
TRAP (2)
WRITEBACK
N - 3
N - 2
N - 1
Interrupt Response Time
1
0
IR-Flag