
C165H
Parallel Ports
Data Sheet
127
2001-04-19
PRELMNARY
-EXCERPT-
in the following subsections.
On most of the port lines, the user software is responsible for setting the proper direction
when using an alternate input or output function of a pin. This is done by setting or
clearing the direction control bit DPx.y of the pin before enabling the alternate function.
There are port lines, however, where the direction of the port line is switched
automatically. For instance, in the multiplexed external bus modes of PORT0, the
direction must be switched several times for an instruction fetch in order to output the
these cases, the direction of the port line is switched automatically by hardware if the
alternate function of such a pin is enabled.
Note:
In this case, make sure DP0 is set to ’0’ signal.
To determine the appropriate level of the port output latches, check how the alternate
data output is combined with the respective port latch output.
There is one basic structure for all port lines with only an alternate input function. Port
lines with only an alternate output function, however, have different structures due to the
way the direction of the pin is switched and depending on whether the pin is accessible
by the user software or not in the alternate function mode.
All port lines that are not used for these alternate functions may be used as general
purpose I/O lines. When using port pins for general purpose output, the initial output
value should be written to the port latch prior to enabling the output drivers, in order to
avoid undesired transitions on the output pins. This applies to single pins as well as to
pin groups (see examples below).
OUTPUT_ENABLE_SINGLE_PIN:
BSET
P4.0
BSET
DP4.0
;Initial output level is ’high’
;Switch on the output driver
OUTPUT_ENABLE_PIN_GROUP:
BFLDL
P4, #05H, #05H
BFLDL
DP4, #05H, #05H
;Initial output level is ’high’
;Switch on the output drivers
Each of these ports and the alternate input and output functions are described in detail
7.1
PORT0
The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0,
respectively. Both halfs of PORT0 can be written (eg. via a PEC transfer) without
effecting the other half.