
C165H
System Control Unit (CSCU)
Data Sheet
421
2001-04-19
PRELMNARY
the appropriate mode.
The switching between the different security levels is controlled by a state machine. Via
a password and a command sequence the security levels can be changed. After reset
always the unprotected mode is automatically selected. The EINIT command switches
the security level automatically to protected mode.
The low protected mode is especially important for a standby state of the application.
This mode allows fast accesses within two commands to the protected registers without
removing the protection completely.
-EXCERPT-
Note:
The CSCU provides per XPERCON bit one enable signal for XPER visibility
control. These enable signals are routed to the core to be combined with
selectable (per module pins) BUSACT functions of XBCON registers.
19.4
System Control Block
19.4.1
Register Write Protection
The System Control Unit CSCU provides two different protection types of registers:
Unprotected Registers
Protectable Registers
The unprotected registers allow reading and writing (if not read-only) of register values
without any restrictions. However, the write access of the protectable registers (security
registers) can be programmed for three different modes of security level, whereas the
read access is always unprotected:
Write Protected Mode
Low Protected Mode
Unprotected Mode
In write protected mode the registers can not be accessed by a write command. However
in low protected mode the registers can be written with a special command sequence
(see desription below). If the registers are set to unprotected mode, all write accesses
are possible.
Some register controlled functions and modes which are critical for the C165H’s
operation are locked after the execution of EINIT, so these vital system functions cannot
be changed inadvertently eg. by software errors. However, as these security registers
control also the power management they need to be accessed during operation to select
XPER5
5
rw
0
1
IOM-2
module is not visible
IOM-2 is selected and visible
reserved
4..0
rw
0
These bits are reserved and must be set to Zero
Bit Field
Bits
Type Value Description