參數(shù)資料
型號: SAF7118H
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Multistandard video decoder with adaptive comb filter and component video input
封裝: SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù): 91/175頁
文件大?。?/td> 898K
代理商: SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
91 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
10.2 I
2
C-bus details
10.2.1
Subaddress 00h
10.2.2
Subaddress 01h
The programming of the horizontal increment delay is used to match internal processing
delays to the delay of the ADC. Use recommended position only.
[1]
HLNRS = 1 should not be used in combination with WPOFF = 0.
Table 38.
Function
Chip Version (CV) identification; 00h[7:4]; read only register
Logic levels
ID7
Chip Version (CV)
CV3
ID6
CV2
ID5
CV1
ID4
CV0
Table 39.
Bit
D6
Horizontal increment delay; 01h[6:0]
Description
white peak control off
Symbol
WPOFF
[1]
Value
0
Function
white peak control active (ADC signal is
attenuated, if nominal luminance output
white level is exceeded)
white peak control disabled
off
±
1 LSB
±
2 LSB
±
3 LSB
no update
minimum delay
recommended position
maximum delay
1
00
01
10
11
1111
1110
0111
0000
D[5:4]
update hysteresis for 9-bit
gain; see
Figure 9
GUDL[1:0]
D[3:0]
increment delay
IDEL[3:0]
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