參數(shù)資料
型號(hào)： SAF7118H
廠商： NXP Semiconductors N.V.
元件分類： 通用總線功能
英文描述： Multistandard video decoder with adaptive comb filter and component video input
封裝： SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù)： 73/175頁
文件大小： 898K
代理商： SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
73 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
[1]
Pin numbers for QFP160 in parenthesis.
9.5.1
X port configured as output
If data output is enabled at the expansion port, then the data stream from the decoder is
presented. The data format of the 8-bit data bus is dependent on the chosen data type,
selectable by the line control registers LCR2 to LCR24; see
Table 7
. In contrast to the
image port, the sliced data format is not available on the expansion port. Instead, raw
CVBS samples are always transferred if any sliced data type is selected.
Some details of data types on the expansion port are as follows:
Active video
(data type 15): contains component Y-C
B
-C
R
4 : 2 : 2 signal, 720 active
pixels per line. The amplitude and offsets are programmable via DBRI7 to DBRI0,
DCON7 to DCON0, DSAT7 to DSAT0, OFFU1, OFFU0, OFFV1 and OFFV0. The
nominal levels are illustrated in
Figure 19
.
Test line
(data type 6): is similar to the active video format, with some constraints
within the data processing:
–
Adaptive chrominance comb filter, vertical filter (chrominance comb filter for NTSC
standards, PAL phase error correction) within the chrominance processing are
disabled
Table 28.
Symbol Pin
[1]
XPD7to
XPD0
Signals dedicated to the expansion port
I/O
Description
C11, A11,
B10, A10, B9,
A9,B8 and A8
(127, 128,
130, 131, 134,
135, 138 and
139)
A7 (143)
I/O
Bit
OFTS[2:0] 13h[2:0],
91h[7:0] and
C1h[7:0]
I/O
X port data: in output mode controlled by
decoder section, data format see
Table 29
;
in input mode Y-C
B
-C
R
4 : 2 : 2 serial input
data or luminance part of a 16-bit
Y-C
B
-C
R
4 : 2 : 2 input
XCLK
clock at expansion port: if output, then
copy of LLC; as input normally a double
pixel clock of up to 32 MHz or a gated
clock (clock gated with a qualifier)
data valid flag of the expansion port input
(qualifier): if output, then decoder
(HREF and VGATE) gate; see
Figure 34
data request flag = ready to receive, to
work with optional buffer in external
device, to prevent internal buffer overflow;
second function: input related task flag
A/B
horizontal reference signal for the X port:
as output: HREF or HS from the decoder
(see
Figure 34
); as input: a reference edge
for horizontal input timing and a polarity for
input field ID detection can be defined
vertical reference signal for the X port: as
output: V123 or field ID from the decoder
(see
Figure 32
and
Figure 33
); as input: a
reference edge for vertical input timing and
for input field ID detection can be defined
port control: switches X port input 3-state
XCKS[92h[0]]
XDQ
B7 (144)
I/O
-
XRDY
A6 (146)
O
XRQT[83h[2]]
XRH
C7 (141)
I/O
XRHS[13h[6]],
XFDH[92h[6]] and
XDH[92h[2]]
XRV
D8 (140)
I/O
XRVS[1:0] 13h[5:4],
XFDV[92h[7]] and
XDV[1:0] 92h[5:4]
XTRI
B11 (126)
I
XPE[1:0] 83h[1:0]
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