參數(shù)資料
型號： SAF7118H
廠商： NXP Semiconductors N.V.
元件分類： 通用總線功能
英文描述： Multistandard video decoder with adaptive comb filter and component video input
封裝： SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù)： 143/175頁
文件大小： 898K
代理商： SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
143 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
[1]
All X values must be set to logic 0.
11.3 Audio clock generation part
The given values force the following behavior of the SAF7118 audio clock generation part:
Used crystal is 24.576 MHz
Expected field frequency is 59.94 Hz (e.g. NTSC M standard)
Generated audio master clock frequency at pin AMCLK is
256
×
44.1 kHz = 11.2896 MHz
AMCLK is externally connected to AMXCLK [short-cut between pins P11 (72) and
M12 (76)]
ASCLK = 32
×
44.1 kHz = 1.4112 MHz
ALRCLK is 44.1 kHz
[1]
All X values must be set to logic 0.
2B
2C
2D
2E
2F
component contrast control
component saturation control
interrupt mask 1
interrupt mask 2
interrupt mask 3
CCON7 to CCON0
CSAT7 to CSAT0
X, X, X, MVPSV, MPPV, MCCV, X and MERROF
X, MHLCK, X, X, X, X, MDCSTD1 and MDCSTD0
MINTL, MHLVLN, MFIDT, X, MTYPE3, MCOLSTR,
MCOPRO and MRDCAP
40
47
00
00
00
Table 140. Component video part and interrupt mask start setup values
…continued
Subaddress
(hexadecimal)
Register function
Bit name
[1]
Values
(hexadecimal)
Table 141. Audio clock part setup values
Subaddress
(hexadecimal)
Register function
Bit name
[1]
Values (binary)
7 6 5 4 3 2 1 0
1 0 1 1 1 1 0 0 BC
Start
(hexadecimal)
30
audio master clock cycles per
field; bits D7 to D0
audio master clock cycles per
field; bits D15 to D8
audio master clock cycles per
field; bits D17 and D16
reserved
audio master clock nominal
increment; bits D7 to D0
audio master clock nominal
increment; bits D15 to D8
audio master clock nominal
increment; bits D21 to D16
reserved
clock ratio AMXCLK to ASCLK X, X, SDIV5 to SDIV0
clock ratio ASCLK to ALRCLK
audio clock generator basic
setup
reserved
ACPF7 to ACPF0
31
ACPF15 to ACPF8
1 1 0 1 1 1 1 1 DF
32
X, X, X, X, X, X, ACPF17
and ACPF16
X, X, X, X, X, X, X, X
ACNI7 to ACNI0
0 0 0 0 0 0 1 0 02
33
34
0 0 0 0 0 0 0 0 00
1 1 0 0 1 1 0 1 CD
35
ACNI15 to ACNI8
1 1 0 0 1 1 0 0 CC
36
X, X, ACNI21 to ACNI16
0 0 1 1 1 0 1 0 3A
37
38
39
3A
X, X, X, X, X, X, X, X
0 0 0 0 0 0 0 0 00
0 0 0 0 0 0 1 1 03
0 0 0 1 0 0 0 0 10
0 0 0 0 0 0 0 0 00
X, X, LRDIV5 to LRDIV0
X, X, X, X, APLL, AMVR, LRPH,
SCPH
X, X, X, X, X, X, X, X
3B to 3F
0 0 0 0 0 0 0 0 00
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