參數(shù)資料
型號： SAF7118H
廠商： NXP Semiconductors N.V.
元件分類： 通用總線功能
英文描述： Multistandard video decoder with adaptive comb filter and component video input
封裝： SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù)： 32/175頁
文件大?。?/td> 898K
代理商： SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
32 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
8.1.3
Synchronization
The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is
further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the
phase detectors where they are compared with the sub-divided clock frequency. The
resulting output signal is applied to the loop filter to accumulate all phase deviations.
Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end
requirements. The loop filter signal drives an oscillator to generate the Line Frequency
COntrol (LFCO) signal; see
Figure 21
.
The detection of ‘pseudo syncs’ as part of the Macrovision copy protection standard is
also achieved within the synchronization circuit.
The result is reported as flag COPRO within the decoder status byte at subaddress 1Fh.
8.1.4
Clock generation circuit
The internal CGC generates all clock signals required for the video input processor.
The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal
PLL. It is the multiple of the line frequency:
6.75 MHz = 429
×
f
H
(50 Hz), or
6.75 MHz = 432
×
f
H
(60 Hz)
The LFCO signal is multiplied by a factor of 2 and 4 in the internal PLL circuit (including
phase detector, loop filtering, VCO and frequency divider) to obtain the output clock
signals. The rectangular output clocks have a 50 % duty factor.
CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128.
Equation for modification of the raw data levels via bytes RAWG and RAWO:
It should be noted that the resulting levels are limited to 1 to 254 in accordance with “ITU
Recommendation 601/656”
a. Sources containing 7.5 IRE black
level offset (e.g. NTSC M).
b. Sources not containing black level
offset.
Fig 20. CVBS (raw data) range for scaler input, data slicer and X port output
LUMINANCE
+
255
+
209
+
71
+
60
1
white
sync bottom
black shoulder
black
SYNC
001aac244
LUMINANCE
+
255
+
199
+
60
1
white
sync bottom
black shoulder = black
SYNC
001aac245
CVBS
OUT
IntRAWG
-----------------
64
CVBS
nom
128
–
(
)
×
RAWO
+
=
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相關代理商/技術參數(shù)
參數(shù)描述
SAF7118H/V1,557 功能描述:視頻 IC COMPONENT VID DECODR RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
SAF7129AH 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder
SAF7129AH/V1 功能描述:視頻 IC 6 DAC VIDEO ENCODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
SAF7129AH/V1,518 功能描述:視頻 IC 6 DAC VIDEO ENCODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
SAF7129AH/V1,557 功能描述:視頻 IC 6 DAC VIDEO ENCODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
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