參數(shù)資料
型號: SAF7118H
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Multistandard video decoder with adaptive comb filter and component video input
封裝: SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù): 114/175頁
文件大?。?/td> 898K
代理商: SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
114 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
[1]
Function of HL is selectable via HLSEL[13h[3]]:
HLSEL = 0: HL is standard horizontal lock indicator.
HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable time base e.g. VCRs).
Table 57.
The polarity of any signal on RTS1 can be inverted via RTP1[11h[6]].
RTS1 output
3-state
Constant LOW
CREF (13.5 MHz toggling pulse; see
Figure 34
)
CREF2 (6.75 MHz toggling pulse; see
Figure 34
)
HL; horizontal lock indicator
[1]
:
HL = 0: unlocked
HL = 1: locked
VL; vertical and horizontal lock:
VL = 0: unlocked
VL = 1: locked
DL; vertical and horizontal lock and color detected:
DL = 0: unlocked
DL = 1: locked
Reserved
HREF, horizontal reference signal; indicates 720 pixels valid data
on the expansion port. The positive slope marks the beginning of a
new active line. HREF is also generated during the vertical
blanking interval (see
Figure 34
).
HS:
Programmable width in LLC8 steps via HSB[7:0] 06h[7:0] and
HSS[7:0] 07h[7:0]
Fine position adjustment in LLC2 steps via HDEL[1:0] 11h[5:4]
(see
Figure 34
)
HQ; HREF gated with VGATE
Reserved
V123; vertical sync; see vertical timing diagrams
Figure 32
and
Figure 33
VGATE; programmable via VSTA[8:0] 17h[0] 15h[7:0], VSTO[8:0]
17h[1] 16h[7:0] and VGPS[17h[2]]
Reserved
FID; position programmable via VSTA[8:0] 17h[0] 15h[7:0]; see
vertical timing diagrams
Figure 32
and
Figure 33
RT signal control: RTS1 output; 12h[7:4]
RTSE13
0
0
0
0
0
RTSE12
0
0
0
0
1
RTSE11
0
0
1
1
0
RTSE10
0
1
0
1
0
0
1
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
1
1
1
1
0
0
1
1
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1
0
1
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