- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98069 > S3C3410XXX-QA 32-BIT, MROM, 40 MHz, RISC MICROCONTROLLER, PQFP128 PDF資料下載
參數(shù)資料
| 型號(hào)： | S3C3410XXX-QA |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 40 MHz, RISC MICROCONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, QFP-128 |
| 文件頁(yè)數(shù)： | 92/314頁(yè) |
| 文件大?。?/td> | 1701K |
| 代理商： | S3C3410XXX-QA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)當(dāng)前第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)第305頁(yè)第306頁(yè)第307頁(yè)第308頁(yè)第309頁(yè)第310頁(yè)第311頁(yè)第312頁(yè)第313頁(yè)第314頁(yè)
S3C3410X RISC MICROPROCESSOR
DMA
6-3
Starting/Stopping DMA Transfer
The DMA can start its operation of transferring the data when the DMA controller receives the request from the
nDREQ signal through external pin, request from UART, request from SIO, or request from Timer1/3. In case of
data transfer between memories, the DMA can also start its operation when the user write the start bit(Run bit) in
DMA control register. When the entire data transfer specified in DMACNT has been finished, the DMA goes into
the idle mode. If users want to perform another DMA operation, the configuration of DMA operation should be
programmed again. The users can stop the DMA operation before its complete termination. By clearing the start
bit(Run bit), the users can stop the DMA operation even if the specified DMA operation is not finished. When
users stop the DMA operation, there will be interrupt generation which depends on the SI(Stop Interrupt) bit in
DMA control register. If SI bit is 0 in DMA control register, there will be DMA operation stop without the interrupt
generation. If users want to resume the DMA operation, users should re-run the DMA operation by setting the
start bit(RE bit) in DMA control register. To guarantee the complete DMA re-run, users should not change the
DMA configuration before the re-start.
DATA TRANSFER MODE
Single Step Mode
The single step mode is usually used for test or debugging because the bus mastership can be handed over to
other bus master between Read and Write. For the initiation of DMA operation, we need the activation of nDREQ
for each Read and Write cycle and there should be separate activation of nDACK for each Read and Write cycle.
In other word, we need two times DMA request and two times DMA acknowledge for single DMA operation. For
this reason, this kind of DMA operation is too slow and this is only for debugging purpose. During the inactive
period of nXDACK, i.e., between Read and Write cycle, the bus controller re-evaluates the bus priority to
determine the new bus mastership.
When the DMA request signal goes low, the bus controller can indicate the bus allocation for the DMA operation
by lowering the DMA Acknowledge signal if there is not higher priority bus request except this DMA request.
During the first low level period of the DMA Acknowledge signal, there will be a DMA read cycle. After the DMA
read cycle, there will be a rising of the DMA Acknowledge signal to indicate the end of the DMA read cycle.
Simultaneously, the next DMA write cycle will happen if the DMA request signal is still low at the rising edge of
DMA acknowledge. But, if the DMA request signal is already high at the rising edge of DMA acknowledge, the
next DMA write cycle will be delayed to the new coming activation of DMA Request signal. The Single Step Mode
of DMA operation can be initiated by the request from UART or SIO or Timer1/3 as well as nDREQ.
nDREQ
nDACK
RD/WR Cycle
Figure 6-2. External DMA requests (Single Mode)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S3C70F2XX-SO | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO32 |
| S3C70F4XX-AV | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP30 |
| S3C72M9XX-QA | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP128 |
| S3P72M9-QA | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP128 |
| S3C7414XX-AQ | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP42 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S3-C3-5V | 制造商:Panasonic Electric Works 功能描述: |
| S3C380D | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:Samsung S3C380D 16/32-bit RISC microcontroller is a cost-effective and high-performance microcontroller solution for TV applications. |
| S3C44B0X | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:RISC MICROPROCESSOR |
| S3C44B0X01 | 制造商:Samsung Semiconductor 功能描述:3C44B0X01 |
| S3C44B0X01-ED80 | 制造商:Samsung 功能描述:S3C44B0X01-ED80 - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。