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參數(shù)資料
| 型號(hào)： | S3C3410XXX-QA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 40 MHz, RISC MICROCONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, QFP-128 |
| 文件頁(yè)數(shù)： | 200/314頁(yè) |
| 文件大小： | 1701K |
| 代理商： | S3C3410XXX-QA |
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S3C3410X RISC MICROPROCESSOR
IIC-BUS INTERFACE
14-5
READ-WRITE OPERATION
In case of transmitter mode, after a data was transferred, the IIC-bus interface will wait until IICDS(IIC-bus Data
Shift Register) is written by a new date. Until the new data is written, the SCL line will be held low. After the new
data is written to IICDS register, the SCL line will be released. The S3C3410X should wait the interrupt to know
the completion of transmission of current data. After getting the interrupt request, the CPU should write a new
data into IICDS, again.
In case of receive mode, after a data is received, the IIC-bus interface will wait until IICDS register is read. Until
the new data is read out, the SCL line will be held low. After the new data is read out from IICDS register, the
SCL line will be released. The S3C3410X should wait the interrupt to know the completion of reception of new
data. After getting the interrupt request, the CPU should read data from IICDS.
BUS ARBITRATION PROCEDURES
Arbitration takes place on the SDA line to prevent the contention on the bus between two masters. If a master
with a SDA High level detects another master with a SDA active Low level, it will not indicate a data transfer
because the current level on the bus does not correspond to its own. The arbitration procedure will be extended
until the SDA line will be High.
But, in case of simultaneous lowering of the SDA line from masters, each master should evaluate whether or not
the mastership is allocated to itself. For the purpose of evaluation, each master should detect the address bits.
While each master generate the slaver address, it should also detect the address bit on the SDA line because the
lowering of SDA line is stronger than maintaining High on the line. For example, one master generate Low as first
address bit, while the other master is maintaining High. In this case, both master will be detect Low on the bus
because Low is stronger than High even if first master is trying to maintain High on the line. In this case, Low-
generating master as first address bit will get the mastership and High-generating master as first address bit
should withdraw the mastership. If both master generate Low as first address bit, there should be arbitration for
second address bit, again. This arbitration will be continued up to the end of last address bit.
ABORT CONDITION
If a slave receiver can not acknowledge the confirmation of the slave address, it should hold the level of the SDA
line High. In this case, the master should generate a Stop condition to abort the transfer.
If a master receiver is involved in the aborted transfer, it should signal the end of the slave transmit operation. It
does this by canceling the generation of an ACK in the master Rx mode. The slave transmitter should then
release the SDA to allow a master to generate a Stop condition.
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| S3C72M9XX-QA | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP128 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S3-C3-5V | 制造商:Panasonic Electric Works 功能描述: |
| S3C380D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Samsung S3C380D 16/32-bit RISC microcontroller is a cost-effective and high-performance microcontroller solution for TV applications. |
| S3C44B0X | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:RISC MICROPROCESSOR |
| S3C44B0X01 | 制造商:Samsung Semiconductor 功能描述:3C44B0X01 |
| S3C44B0X01-ED80 | 制造商:Samsung 功能描述:S3C44B0X01-ED80 - Trays |
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