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參數(shù)資料
| 型號(hào)： | S3C3410XXX-QA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 40 MHz, RISC MICROCONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, QFP-128 |
| 文件頁(yè)數(shù)： | 170/314頁(yè) |
| 文件大?。?/td> | 1701K |
| 代理商： | S3C3410XXX-QA |
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S3C3410X RISC MICROPROCESSOR
INTERRUPT CONTROLLER
11-1
11
INTERRUPT CONTROLLER
OVERVIEW
In S3C3410X, there are 35 interrupt sources. Among them, 23 interrupt sources are coming from internal
peripheral devices like the DMA controller, UART, SIO, etc. Other 8 interrupt sources are coming from external
interrupt request pins like EINT0, EINT1, EINT2, EINT3, EINT8, EINT9, EINT10, and EINT11. The other 4 are
coming from external interrupt request pins like EINT4, EINT5, EINT6, and EINT7. Because these 4 external
interrupt requests should be OR-ed internally, we consider these external interrupt request sources as one
interrupt request source to CPU. In other word, the total interrupt request sources to CPU is 32, not 35.
Even if there are many interrupt request sources, the ARM7TDMI core can only recognize all interrupt as two
kinds of interrupt: a normal interrupt request(IRQ) and a fast interrupt request(FIQ). Therefore, all interrupt
sources in S3C3410X should be categorized as either IRQ or FIQ.
The multiple interrupt sources should be controlled by three kind of information in special registers in interrupt
controller. These are INTMOD, INTPND, and INTMSK register. The role of three registers in interrupt controller is
as follow.
In S3C3410X, the interrupt controller can support the interrupt base vector address as well as programmable
priority. To reduce the interrupt latency, the interrupt controller in S3C3410X can assign the hard-wired vector
address for each interrupt source. The total 32 interrupt request sources to CPU can have the programmable
priority. This kind of programmable priority can make users to have more intelligent interrupt handling.
Interrupt Mode Register: Defines the interrupt mode for each interrupt source, which is IRQ or FIQ. By
having the configuration for each interrupt source in this register, users can allocate all interrupt sources as
IRQ or FIQ mode interrupt.
Interrupt Pending Register: In CPU core, there is PSR(Processor Status Register) register, which has
several field including the interrupt relating I-Flag and F-Flag. As mentioned above, the CPU can accept two
kinds of interrupt even if there are many interrupt sources in S3C3410X. That is why all interrupt sources in
S3C3410X should be categorized into two mode, which is IRQ mode and FIQ mode. In this case, if CPU is
running the service for certain interrupt, and if this interrupt has IRQ mode, the other interrupt sources with
IRQ mode can not be serviced until the completion of current service. These interrupt should be pending in
IPR(Interrupt Pending Register). In case of FIQ mode, other FIQ interrupt request can not take CPU while the
current FIQ service is running as same as IRQ case. Therefore, the FIQ interrupt request should be pending in
IPR as same as IRQ. If IRQ interrupt service is running, the FIQ interrupt can take the CPU for service
because FIQ has higher priority than IRQ. In other word, ARM CPU can support two level interrupt
architecture. The pending interrupt service can start whenever the I-Flag or F-Flag should be cleared to "0".
The service routine should clear the pending bit, also.
Interrupt Mask Register: If this mask bit is set, the corresponding interrupt request should be disabled. Users
can select the interrupt enable or disable by using this register. For masking(Disable the interrupt), the
corresponding mask bit should be "0".
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