
S3C3410X RISC MICROPROCESSOR
INTERRUPT CONTROLLER
11-7
INTERRUPT MASK REGISTER (INTMSK)
The interrupt mask register has interrupt mask bits for all interrupt source. When an interrupt source mask bit is
"0", the corresponding interrupt can not be serviced by the CPU when the corresponding interrupt request is
generated. If the mask bit is "1", the interrupt service can be done.
Register
Offset
Address
R/W
Description
Reset
Value
INTMSK
0xc008
R/W
Interrupt mask register.
Each bit can disable or enable the corresponding
interrupt request.
0 = Interrupt service is masked or disabled.
1 = Interrupt service is available
0x0
INTMSK
Bit
Description
Initial State
EINT0
[0]
0 = Masked
1 = Service available
0
EINT1
[1]
0 = Masked
1 = Service available
0
INT_URX
[2]
0 = Masked
1 = Service available
0
INT_UTX
[3]
0 = Masked
1 = Service available
0
INT_UERR
[4]
0 = Masked
1 = Service available
0
INT_DMA0
[5]
0 = Masked
1 = Service available
0
INT_DMA1
[6]
0 = Masked
1 = Service available
0
INT_TOF0
[7]
0 = Masked
1 = Service available
0
INT_TMC0
[8]
0 = Masked
1 = Service available
0
INT_TOF1
[9]
0 = Masked
1 = Service available
0
INT_TMC1
[10]
0 = Masked
1 = Service available
0
INT_TOF2
[11]
0 = Masked
1 = Service available
0
INT_TMC2
[12]
0 = Masked
1 = Service available
0
INT_TOF3
[13]
0 = Masked
1 = Service available
0
INT_TMC3
[14]
0 = Masked
1 = Service available
0
INT_TOF4
[15]
0 = Masked
1 = Service available
0
INT_TMC4
[16]
0 = Masked
1 = Service available
0
INT_BT
[17]
0 = Masked
1 = Service available
0
INT_SIO0
[18]
0 = Masked
1 = Service available
0
INT_SIO1
[19]
0 = Masked
1 = Service available
0
INT_IIC
[20]
0 = Masked
1 = Service available
0
INT_RTCA
[21]
0 = Masked
1 = Service available
0