- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374663 > S29PL064J (Spansion Inc.) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control PDF資料下載
參數(shù)資料
| 型號： | S29PL064J |
| 廠商： | Spansion Inc. |
| 英文描述： | CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| 中文描述： | 3.0伏的CMOS只，同步讀/寫閃存與增強(qiáng)VersatileIO控制記憶 |
| 文件頁數(shù)： | 70/106頁 |
| 文件大?。?/td> | 1997K |
| 代理商： | S29PL064J |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁當(dāng)前第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
68
S29PL127J/S29PL129J/S29PL064J/S29PL032J
31107A62 April 7, 2005
P R E L I M I N A R Y
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command.
Table 21
shows the address
and data requirements for the sector erase command sequence.
The device does
not
require the system to preprogram prior to erase. The Em-
bedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 μs occurs.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 μs, otherwise erasure
may begin. Any sector erase address and command following the exceeded
time-out may or may not be accepted. It is recommended that processor inter-
rupts be disabled during this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase command is written.
If
any command other than 30h, B0h, F0h is input during the time-out pe-
riod, the normal operation will not be guaranteed.
The system must rewrite
the command sequence and any additional addresses and commands.
Note that
SecSi Sector, autoselect, and CFI functions are unavailable when a [pro-
gram/erase] operation is in progress.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See the section on DQ3: Sector Erase Timer). The time-out begins from the ris-
ing edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading
array data and addresses are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the "
Write Operation
Status" section
section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a
hardware reset
im-
mediately
terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
5 illustrates the algorithm for the erase operation. Refer to the "
Erase/Program
Operations
" section tables in the AC Characteristics section for parameters, and
Figure 16
section for timing diagrams.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29PL127J | CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL127J55 | CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL127J60 | CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL127J65 | CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL127J70 | CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29PL064J55BFI120 | 功能描述:閃存 64Mb 3V 55ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| S29PL064J60BAI120 | 制造商:Spansion 功能描述:FLASH MEM PARALLEL 2.7V TO 3.6V 64M-BIT 4M X 16 60NS 48-PIN - Trays |
| S29PL064J60BFI120 | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 64MBIT 4MX16 60NS 48FBGA - Trays |
| S29PL064J60BFI120(E) | 制造商:Spansion 功能描述:Cut Tape |
| S29PL064J60BFW120 | 制造商:Spansion 功能描述:64M (4MX16) 3V, PAGE MODE, HAZMAT - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。