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參數(shù)資料
| 型號： | S29PL064J |
| 廠商： | Spansion Inc. |
| 英文描述： | CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| 中文描述： | 3.0伏的CMOS只，同步讀/寫閃存與增強(qiáng)VersatileIO控制記憶 |
| 文件頁數(shù)： | 24/106頁 |
| 文件大?。?/td> | 1997K |
| 代理商： | S29PL064J |
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22
S29PL127J/S29PL129J/S29PL064J/S29PL032J
31107A62 April 7, 2005
P R E L I M I N A R Y
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the OE# and appro-
priate CE# pins (For PL129J - CE1#/CE2# pins) to V
IL
. In PL129J, CE1# and
CE2# are the power control and select the lower (CE1#) or upper (CE2#) halves
of the device. CE# is the power control. OE# is the output control and gates array
data to the output pins. WE# should remain at V
IH
.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until the command register
contents are altered.
Refer to
Table 33
for timing specifications and to
Figure 11
for the timing diagram.
I
CC1
in the DC Characteristics table represents the active current specification for
reading array data.
Random Read (Non-Page Read)
Address access time (t
ACC
) is equal to the delay from stable addresses to valid
output data. The chip enable access time (t
CE
) is the delay from the stable ad-
dresses and stable CE# to valid data at the output inputs. The output enable
access time is the delay from the falling edge of the OE# to valid data at the out-
put inputs (assuming the addresses have been stable for at least t
ACC
–t
OE
time).
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. Address bits Amax–A3 select an 8 word page,
and address bits A2–A0 select a specific word within that page. This is an asyn-
chronous operation with the microprocessor supplying the specific word location.
The random or initial page access is t
ACC
or t
CE
and subsequent page read ac-
cesses (as long as the locations specified by the microprocessor falls within that
page) is equivalent to t
PACC
. When CE# (CE1# and CE#2 in PL129J) is deasserted
(=V
IH
), the reassertion of CE# (CE1# or CE#2 in PL129J) for subsequent access
has access time of t
ACC
or t
CE
. Here again, CE# (CE1# /CE#2 in PL129J)selects
the device and OE# is the output control and should be used to gate data to the
output inputs if the device is selected. Fast page mode accesses are obtained by
keeping Amax–A3 constant and changing A2–A0 to select the specific word within
that page.
Table 3.
Page Select
Word
A2
A1
A0
Word 0
0
0
0
Word 1
0
0
1
Word 2
0
1
0
Word 3
0
1
1
Word 4
1
0
0
Word 5
1
0
1
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相關(guān)代理商/技術(shù)參數(shù) |
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| S29PL064J55BFI120 | 功能描述:閃存 64Mb 3V 55ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| S29PL064J60BAI120 | 制造商:Spansion 功能描述:FLASH MEM PARALLEL 2.7V TO 3.6V 64M-BIT 4M X 16 60NS 48-PIN - Trays |
| S29PL064J60BFI120 | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 64MBIT 4MX16 60NS 48FBGA - Trays |
| S29PL064J60BFI120(E) | 制造商:Spansion 功能描述:Cut Tape |
| S29PL064J60BFW120 | 制造商:Spansion 功能描述:64M (4MX16) 3V, PAGE MODE, HAZMAT - Trays |
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