參數(shù)資料
型號(hào): S29PL032J65BFI150
廠商: SPANSION LLC
元件分類(lèi): PROM
英文描述: 2M X 16 FLASH 3V PROM, 65 ns, PBGA56
封裝: 7 X 9 MM, LEAD FREE, FBGA-56
文件頁(yè)數(shù): 63/94頁(yè)
文件大小: 949K
代理商: S29PL032J65BFI150
64
S29PL-J
S29PL-J_00_A8 July 29, 2005
Ad van c e
Inf o rmation
Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2,
DQ3, DQ5, DQ6, and DQ7. Table 23 and the following subsections describe the function of these
bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation
is complete or in progress. The device also provides a hardware-based output signal, RY/BY#,
to determine whether an Embedded Program or Erase operation is in progress or has been
completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase
algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is
valid after the rising edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.
When the Embedded Program algorithm is complete, the device outputs the datum programmed
to DQ7. The system must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# Polling on DQ7 is active for approxi-
mately 1 s, then that bank returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embed-
ded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling
produces a “1” on DQ7. The system must provide an address within any of the sectors selected
for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately 400 s, then the bank returns to the read
mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that are protected. However, if the system reads
DQ7 at an address within a protected sector, the status may not be valid.
When the system detects DQ7 has changed from the complement to true data, it can read valid
data at DQ15–DQ0 on the following read cycles. Just prior to the completion of an Embedded
Program or Erase operation, DQ7 may change asynchronously with DQ15–DQ0 while Output En-
able (OE#) is asserted low. That is, the device may change from providing status information to
valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the
status or valid data. Even if the device has completed the program or erase operation and DQ7
has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 will
appear on successive read cycles.
Table 23 shows the outputs for Data# Polling on DQ7. Figure 11 shows the Data# Polling algo-
rithm. Figure 23 in the AC Characteristic section shows the Data# Polling timing diagram.
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