參數(shù)資料
型號(hào): S29PL032J65BFI150
廠商: SPANSION LLC
元件分類: PROM
英文描述: 2M X 16 FLASH 3V PROM, 65 ns, PBGA56
封裝: 7 X 9 MM, LEAD FREE, FBGA-56
文件頁數(shù): 58/94頁
文件大?。?/td> 949K
代理商: S29PL032J65BFI150
July 29, 2005 S29PL-J_00_A8
S29PL-J
59
Advance
Information
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by
writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are writ-
ten, and are then followed by the address of the sector to be erased, and the sector erase
command. Table 21 shows the address and data requirements for the sector erase command
sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase al-
gorithm automatically programs and verifies the entire memory for an all zero data pattern prior
to electrical erase. The system is not required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-out of 50 s occurs. During the
time-out period, additional sector addresses and sector erase commands may be written. Load-
ing the sector erase buffer may be done in any sequence, and the number of sectors may be
from one sector to all sectors. The time between these additional cycles must be less than 50
s, otherwise erasure may begin. Any sector erase address and command following the ex-
ceeded time-out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled
after the last Sector Erase command is written. If any command other than 30h, B0h, F0h
is input during the time-out period, the normal operation will not be guaranteed. The
system must rewrite the command sequence and any additional addresses and commands. Note
that Secured Silicon Sector, autoselect, and CFI functions are unavailable when a [pro-
gram/erase] operation is in progress.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the sec-
tion on DQ3: Sector Erase Timer). The time-out begins from the rising edge of the final WE#
pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and
addresses are no longer latched. Note that while the Embedded Erase operation is in progress,
the system can read data from the non-erasing bank. The system can determine the status of
the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write
Operation Status section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored. However, note that a hardware reset immediately terminates the erase
operation. If that occurs, the sector erase command sequence should be reinitiated once that
bank has returned to reading array data, to ensure data integrity.
10 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables
in the AC Characteristics section for parameters, and Figure 21 section for timing diagrams.
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