參數(shù)資料
型號： S29PL032J65BFI150
廠商： SPANSION LLC
元件分類： PROM
英文描述： 2M X 16 FLASH 3V PROM, 65 ns, PBGA56
封裝： 7 X 9 MM, LEAD FREE, FBGA-56
文件頁數(shù)： 13/94頁
文件大小： 949K
代理商： S29PL032J65BFI150
18
S29PL-J
S29PL-J_00_A8 July 29, 2005
Ad van c e
Inf o rmation
Refer to Table 32 for timing specifications and to Figure 16 for the timing diagram. ICC1 in the DC
Characteristics table represents the active current specification for reading array data.
Random Read (Non-Page Read)
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The
chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data
at the output inputs. The output enable access time is the delay from the falling edge of the OE#
to valid data at the output inputs (assuming the addresses have been stable for at least tACC–tOE
time).
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM
read operation. This mode provides faster read access speed for random locations within a page.
Address bits Amax–A3 select an 8 word page, and address bits A2–A0 select a specific word
within that page. This is an asynchronous operation with the microprocessor supplying the spe-
cific word location.
The random or initial page access is tACC or tCE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When
CE# (CE1# and CE#2 in PL129J) is deasserted (=VIH), the reassertion of CE# (CE1# or CE#2
in PL129J) for subsequent access has access time of tACC or tCE. Here again, CE# (CE1# /CE#2
in PL129J)selects the device and OE# is the output control and should be used to gate data to
the output inputs if the device is selected. Fast page mode accesses are obtained by keeping
Amax–A3 constant and changing A2–A0 to select the specific word within that page.
Simultaneous Read/Write Operation
In addition to the conventional features (read, program, erase-suspend read, erase-suspend
program, and program-suspend read), the device is capable of reading data from one bank of
memory while a program or erase operation is in progress in another bank of memory (simulta-
neous operation). The bank can be selected by bank addresses (PL127J: A22–A20, PL129J and
PL064J: A21–A19, PL032J: A20–A18) with zero latency.
The simultaneous operation can execute multi-function mode in the same bank.
Table 3 Page Select
Word
A2
A1
A0
Word 0
0
Word 1
0
1
Word 2
0
1
0
Word 3
0
1
Word 4
1
0
Word 5
1
0
1
Word 6
1
0
Word 7
1
Table 4 Bank Select
Bank
PL127J: A22–A20, PL064J: A21–A19, PL032J: A20–A18
Bank A
000
Bank B
001, 010, 011
Bank C
100, 101, 110
Bank D
111
Bank
CE1#
CE2#
PL129J: A21–A20
Bank 1A
0
1
00
Bank 1B
0
1
01, 10, 11
Bank 2A
1
0
00, 01, 10
Bank 2B
1
0
11
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