參數(shù)資料
型號： S29GL064M90TAIR42
廠商： SPANSION LLC
元件分類： DRAM
英文描述： 256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology
中文描述： 4M X 16 FLASH 3V PROM, 90 ns, PDSO48
封裝： MO-142-EC, TSOP-48
文件頁數(shù)： 4/116頁
文件大?。?/td> 1656K
代理商： S29GL064M90TAIR42
2
S29GL-M MirrorBit
TM
Flash Family
S29GL-M_00_B6 October 10, 2006
D a t a S h e e t
General Description
The S29GL256/128/064/032M family of devices are 3.0 V single power Flash memory manufac-
tured using 0.23 μm MirrorBit technology. The S29GL256M is a 256Mbit, organized as 16,777,216
words or 33,554,432 bytes. The S29GL128M is a 128 Mbit, organized as 8,388,608 words or
16,777,216 bytes. The S29GL064M is a 64 Mbit, organized as 4,194,304 words or 8,388,608 bytes.
The S29GL032M is a 32 Mbit, organized as 2,097,152 words or 4,194,304 bytes. Depending on the
model number, the devices have an 8-bit wide data bus only, 16-bit wide data bus only, or a 16-bit
wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The devices
can be programmed either in the host system or in standard EPROM programmers.
Access times as fast as 90 ns (S29GL128M, S29GL064M, S29GL032M) or 100 ns (S29GL256M) are
available. Note that each access time has a specific operating voltage range (V
CC
) as specified in
Product Selector Guide
and the
Ordering Information
sections starting on
page 16
. Package offer-
ings include 40-pin TSOP, 48-pin TSOP, 56-pin TSOP, 48-ball fine-pitch BGA, 63-ball fine-pitch BGA
and 64-ball Fortified BGA, depending on model number. Each device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a
single 3.0 volt pow er supply
for both read and write functions. In
addition to a V
CC
input, a high-voltage
accelerated program ( ACC)
feature provides shorter pro-
gramming times through increased current on the WP#/ACC input. This feature is intended to
facilitate factory throughput during system production, but may also be used in the field if desired.
The device is entirely command set compatible with the
J EDEC single-pow er-supply Flash stan-
dard
. Commands are written to the device using standard microprocessor write timing. Write cycles
also internally latch addresses and data needed for the programming and erase operations.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without
affecting the data contents of other sectors. The device is fully erased when shipped from the
factory.
Device programming and erasure are initiated through command sequences. Once a program or
erase operation starts, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle)
sta-
tus bits
or monitor the
Ready/ Busy# ( RY / BY # )
output to determine whether the operation is
complete. To facilitate programming, an
Unlock Bypass
mode reduces command sequence over-
head by requiring only two write cycles to program data instead of four.
Hardw are data protection
measures include a low V
CC
detector that automatically inhibits write
operations during power transitions. The hardware sector protection feature disables both program
and erase operations in any combination of sectors of memory. This can be achieved in-system or
via programming equipment.
The
Erase Suspend/ Erase Resume
feature allows the host system to pause an erase operation
in a given sector to read or program any other sector and then complete the erase operation. The
Program Suspend/ Program Resume
feature enables the host system to pause a program op-
eration in a given sector to read any other sector and then complete the program operation.
The
hardw are RESET# pin
terminates any operation in progress and resets the device, after
which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry.
A system reset would thus also reset the device, enabling the host system to read boot-up firmware
from the Flash memory device.
The device reduces power consumption in the
standby mode
when it detects specific voltage levels
on CE# and RESET#, or when addresses are stable for a specified period of time.
The
W rite Protect ( W P# )
feature protects the first or last sector by asserting a logic low on the
WP#/ACC pin or WP# pin, depending on model number. The protected sector is still protected even
during accelerated programming.
The
Secured Silicon Sector
provides a 128-word/256-byte area for code or data that can be per-
manently protected. Once this sector is protected, no further changes within the sector can occur.
Spansion MirrorBit flash technology combines years of Flash memory manufacturing experience to
produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases
all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using
hot electron injection.
相關(guān)PDF資料
PDF描述
S29GL064M90TAIR43 256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology
S29GL064M90TAIR70 256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology
S29GL064M90TAIR72 256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology
S29GL064M90TAIR73 256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology
S29GL064M90TAIR80 256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29GL064M90TAIR60 制造商:Spansion 功能描述:Flash Mem Parallel 3.3V 64M-Bit 4M x 16 90ns 48-Pin TSOP Tray
S29GL064M90TAIR70 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 64M-Bit 4M x 16 90ns 48-Pin TSOP Tray
S29GL064M90TFIR20 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 64M-Bit 8M x 8/4M x 16 90ns 56-Pin TSOP Tray
S29GL064M90TFIR30 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 64M-Bit 8M x 8/4M x 16 90ns 48-Pin TSOP Tray
S29GL064M90TFIR4 制造商:Spansion 功能描述:IC,EEPROM,NOR FLASH,4MX16/8MX8,CMOS,TSSOP,48PIN,PLASTIC
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