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參數(shù)資料
| 型號(hào)： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁數(shù)： | 7/159頁 |
| 文件大小： | 1200K |
| 代理商： | S1C63158D0A010P |
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96
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Receive error interrupt factor is generated when a parity error, framing error or overrun error has been
detected during data receiving.
When set in this manner, if the corresponding interrupt enable mask is set to "1" and the CPU is set to
interrupt enabled status (I flag = "1"), an interrupt will be generated to the CPU.
Regardless of the interrupt mask register setting, the interrupt factor flag will be set to "1" by the occurrence
of an interrupt generation condition.
The interrupt factor flag is reset to "0" by writing "1".
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".
4.10.10 Programming notes
(1) Be sure to initialize the serial interface mode in the transmit/receive disabled status (TXENx = RXENx
= "0").
(2) Do not perform double trigger (writing "1") to TXTRGx (RXTRGx) when the serial interface is in the
transmitting (receiving) operation.
(3) In the clock synchronous mode, since one clock line (SCLKx) is shared for both transmitting and
receiving, transmitting and receiving cannot be performed simultaneously. (Half duplex only is
possible in clock synchronous mode.)
Consequently, be sure not to write "1" to RXTRGx (TXTRGx) when TXTRGx (RXTRGx) is "1".
(4) When a parity error or framing error is generated during receiving in the asynchronous mode, the
receiving error interrupt factor flag ISERx is set to "1" prior to the receive completion interrupt factor
flag ISRCx for the time indicated in Table 4.10.10.1. Consequently, when an error is generated, you
should reset the receiving complete interrupt factor flag ISRCx to "0" by providing a wait time in error
processing routines and similar routines.
When an overrun error is generated, the receiving complete interrupt factor flag ISRCx is not set to "1"
and a receiving complete interrupt is not generated.
Table 4.10.10.1 Time difference between ISERx and ISRCx on error generation
Clock source
Time difference
fOSC3 / n
Programmable timer
1/2 cycles of fOSC3 / n
1 cycle of timer 1 underflow
(5) When the demultiplied signal of the OSC3 oscillation circuit is made the clock source, it is necessary
to turn the OSC3 oscillation ON, prior to using the serial interface.
A time interval of 5 msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation
stabilizes, is necessary, due to the oscillation element that is used. Consequently, you should allow an
adequate waiting time after turning ON of the OSC3 oscillation, before starting transmitting/receiv-
ing of serial interface. (The oscillation start time will vary somewhat depending on the oscillator and
on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 7,
"Electrical Characteristics".)
At initial reset, the OSC3 oscillation circuit is set to OFF status.
(6) Be aware that the maximum clock frequency for the serial interface is limited to 2 MHz.
(7) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
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