參數(shù)資料
型號： S1C63158D0A010P
元件分類： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53
封裝： DIE-53
文件頁數(shù)： 129/159頁
文件大?。?/td> 1200K
代理商： S1C63158D0A010P
S1C63808 TECHNICAL MANUAL
EPSON
63
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
The event counter mode also allows use of a noise reject function to eliminate noise such as chattering on
the external clock (K13 input signal). This function is selected by writing "1" to the timer 0 function
selection register FCSEL.
When "with noise rejector" is selected, an input pulse width for both low and high levels must be 0.98
msec
or more to count reliably. The noise rejector allows the counter to input the clock at the second
falling edge of the internal 2,048 Hz
signal after changing the input level of the K13 input port terminal.
Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec
or less.
(
: fOSC1 = 32.768 kHz)
Figure 4.9.4.2 shows the count down timing with noise rejector.
Counter
input clock
2
Counter data
n
n-1
n-2
n-3
EVIN input (K13)
2,048 Hz
1
1 When fOSC1 is 32.768 kHz
2 When PLPOL register is set to "0"
Fig. 4.9.4.2 Count down timing with noise rejector
The operation of the event counter mode is the same as the normal timer except it uses the K13 input as
the clock. Refer to Section 4.9.2, "Basic count operation" for basic operation and control.
4.9.5 16-bit timer (timer 0 + timer 1)
Timers 0 and 1 can be used as a 16-bit timer.
To use the 16-bit timer, write "1" to the timer 0 16-bit mode selection register MOD16.
The 16-bit timer is configured with timer 0 for low-order byte and timer 1 for high-order byte as shown in
Figure 4.9.5.1.
Reload data register
RLD00–RLD07
Data buffer
PTD00–PTD07
PTRUN0
FCSEL
PLPOL
Timer 0 + Timer 1
Timer 0
Timer 1
PTPS00
PTPS01
8-bit
down counter
8-bit
down counter
Prescaler
Selector
CKSEL0
Timer 0 Run/Stop
Clock
control
circuit
Timer function setting
Pulse polarity setting
Prescaler
setting
Under-
flow
signal
Data
bus
Interrupt
TOUT
PTRST0
Timer 0 reset
Low-order 8 bits
High-order 8 bits
Data buffer
PTD10–PTD17
Divider
OSC3
oscillation
circuit
OSC1
oscillation
circuit
fOSC3
fOSC1
Reload data register
RLD10–RLD17
Input port
K13
EVCNT
Event counter mode setting
K13
Fig. 4.9.5.1 Configuration of 16-bit timer
The registers for timer 0 are used to control the timer. Thus the event counter function can also be used.
Timer 1 operates with the timer 0 underflow signal as the count clock, so the clock and RUN/STOP
control registers for timer 1 become invalid.
The counter data in 16-bit mode must be read in the order below.
PTD00–PTD03
→ PTD04–PDT07 → PTD10–PTD13 → PTD14–PTD17
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