參數(shù)資料
型號(hào)： S1C63158D0A010P
元件分類： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53
封裝： DIE-53
文件頁數(shù)： 5/159頁
文件大?。?/td> 1200K
代理商： S1C63158D0A010P
94
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
In the asynchronous system, RXTRGx is used for preparation of the following data receiving. Read the
received data located in the receive data buffer and write "1" into RXTRGx to inform that the receive data
buffer has shifted to empty. When "1" has not been written to RXTRGx, the overrun error flag OERx is set
to "1" at the point where the following receiving has been completed. (When the receiving has been
completed between the operation to read the received data and the operation to write "1" into RXTRGx,
an overrun error occurs.)
In addition, RXTRGx can be read as the status. In either clock synchronous mode or asynchronous mode,
when RXTRGx is set to "1", it indicates receiving operation and when set to "0", it indicates that receiving
has stopped.
At initial reset, RXTRGx is set to "0".
TRXD10–TRXD17: Serial interface 1 transmit/receive data (FF68H, FF69H)
TRXD20–TRXD27: Serial interface 2 transmit/receive data (FF18H, FF19H)
During transmitting
Transmitting data is set.
When "1" is written: High level
When "0" is written: Low level
Write the transmitting data prior to starting transmission.
In the case of continuous transmitting, wait for the transmit completion interrupt, then write the data.
The TRXDx7 becomes invalid for the 7-bit asynchronous mode.
Converted serial data for which the bits set at "1" as high (VDD) level and for which the bits set at "0" as
low (VSS) level are output from the SOUTx terminal.
During receiving
The received data is stored.
When "1" is read: High level
When "0" is read: Low level
The data from the receive data buffer can be read out.
Since the sift register is provided separately from this buffer, reading can be done during a receive opera-
tion in the asynchronous mode. (The buffer function is not used in the clock synchronous mode.)
Read the data after waiting for a receive completion interrupt.
When performing parity check in the 7-bit asynchronous mode, "0" is loaded into the 8th bit (TRXDx7)
that corresponds to the parity bit.
The serial data input from the SINx terminal is level converted, making the high (VDD) level bit "1" and
the low (VSS) level bit "0" and is then loaded into this buffer.
At initial reset, the buffer content is undefined.
OER1: Serial interface 1 overrun error flag (FF67HD0)
OER2: Serial interface 2 overrun error flag (FF17HD0)
Indicates the generation of an overrun error.
When "1" is read: Error
When "0" is read: No error
When "1" is written: Reset to "0"
When "0" is written: Invalid
OERx is an error flag that indicates the generation of an overrun error and becomes "1" when an error has
been generated.
An overrun error is generated when a receiving of data has completed prior to writing "1" to RXTRGx in
the asynchronous mode.
OERx is reset to "0" by writing "1".
OERx is set to "0" at initial reset or when RXENx is set to "0".
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