參數(shù)資料
型號(hào): S1C63158D0A010P
元件分類(lèi): 微控制器/微處理器
英文描述: 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53
封裝: DIE-53
文件頁(yè)數(shù): 146/159頁(yè)
文件大?。?/td> 1200K
代理商: S1C63158D0A010P
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S1C63808 TECHNICAL MANUAL
EPSON
79
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Data transmit procedure
The control procedure and operation during transmitting is as follows.
Data transmitting
End
TXENx
← 0, RXENx ← 0
No
Yes
Transmit complete ?
Set transmitting data
to TRXDx0–TRXDx7
No
Yes
ISTRx = 1 ?
TXENx
← 0
TXTRGx
← 1
TXENx
← 1
No
Yes
Receiver ready ?
In case of master mode
Fig. 4.10.6.2 Transmit procedure in clock synchronous mode
(1) Write "0" in the transmit enable register TXENx and the receive enable register RXENx to reset the
serial interface.
(2) Write "1" in the transmit enable register TXENx to set into the transmitting enable status.
(3) Write the transmitting data into TRXDx0–TRXDx7.
(4) In case of the master mode, confirm the receive ready status on the slave side (external serial
input/output device), if necessary. Wait until it reaches the receive ready status.
(5) Write "1" in the transmit control bit TXTRGx and start transmitting.
In the master mode, this control causes the synchronous clock to change to enable and to be
provided to the shift register for transmitting and output from the SCLKx terminal.
In the slave mode, it waits for the synchronous clock to be input from the SCLKx terminal.
The transmitting data of the shift register shifts one bit at a time at each falling edge of the syn-
chronous clock and is output from the SOUTx terminal. When the final bit is output, the SOUTx
terminal is maintained at that level, until the next transmitting begins.
The transmitting complete interrupt factor flag ISTRx is set to "1" at the point where the data
transmitting of the shift register is completed. When interrupt has been enabled, a transmitting
complete interrupt is generated at this point.
Set the following transmitting data using this interrupt.
(6) Repeat steps (3) to (5) for the number of bytes of transmitting data, and then set the transmit
disable status by writing "0" to the transmit enable register TXENx, when the transmitting is
completed.
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