- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25640 > S1C63158D0A010P 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 PDF資料下載
參數(shù)資料
| 型號(hào)： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁(yè)數(shù)： | 153/159頁(yè) |
| 文件大?。?/td> | 1200K |
| 代理商： | S1C63158D0A010P |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)當(dāng)前第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)
S1C63808 TECHNICAL MANUAL
EPSON
85
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Data receive procedure
The control procedure and operation during receiving is as follows.
End
RXENx
← 1
No
Yes
Receiving interrupt ?
Yes
Receiving complete ?
Received data reading
from TRXDx0–TRXDx7
RXENx
← 0
RXTRGx
← 1
No
Yes
Error generated ?
Error processing
Data receiving
RXENx
← 0
Resets error flags
PERx, OERx and FERx
No
Fig. 4.10.7.3 Receiving procedure in asynchronous mode
(1) Write "0" in the receive enable register RXENx to set the receiving disable status and to reset the
respective PERx, OERx, FERx flags that indicate parity, overrun and framing errors.
(2) Write "1" in the receive enable register RXENx to set into the receiving enable status.
(3) The shift clock will change to enable from the point where the start bit (low) has been input from the
SINx terminal and the receive data will be synchronized to the rising edge following the second
clock, and will thus be successively incorporated into the shift register.
After data bits have been incorporated, the stop bit is checked and, if it is not high, it becomes a framing
error and the error interrupt factor flag ISERx is set to "1". When interrupt has been enabled, an error
interrupt is generated at this point.
When receiving is completed, data in the shift register is transferred to the receive data buffer and the
receiving complete interrupt flag ISRCx is set to "1". When interrupt has been enabled, a receiving
complete interrupt is generated at this point. (When an overrun error is generated, the interrupt
factor flag ISRCx is not set to "1" and a receiving complete interrupt is not generated.)
If "with parity check" has been selected, a parity check is executed when data is transferred into the
receive data buffer from the shift register and if a parity error is detected, the error interrupt factor
flag is set to "1". When the interrupt has been enabled, an error interrupt is generated at this point just
as in the framing error mentioned above.
(4) Read the received data from TRXDx0–TRXDx7 using receiving complete interrupt.
(5) Write "1" to the receive control bit RXTRGx to inform that the receive data has been read out.
When the following data is received prior to writing "1" to RXTRGx, it is recognized as an overrun
error and the error interrupt factor flag is set to "1". When the interrupt has been enabled, an error
interrupt is generated at this point just as in the framing error and parity error mentioned above.
(6) Repeat steps (3) to (5) for the number of bytes of receiving data, and then set the receive disable status
by writing "0" to the receive enable register RXENx, when the receiving is completed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C7XXXF00E199 | 16-BIT, 90 MHz, RISC MICROCONTROLLER, PQFP |
| S2041 | PHOTO TRANSISTOR DETECTOR |
| S3P44R10 | TRIGGER OUTPUT SOLID STATE RELAY, 4000 V ISOLATION-MAX |
| S3S12P128J0VQK | 16-BIT, MROM, 1.05 MHz, MICROCONTROLLER, PQFP80 |
| MC9S12P128J0CFTR | 16-BIT, FLASH, 1.05 MHz, MICROCONTROLLER, QCC48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C63408 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63557D04Q000 | 制造商:Seiko Instruments Inc (SII) 功能描述:EPSON MCU 4BIT |
| S1C63567 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63616 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63632 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。