參數(shù)資料
型號: S1C63158D0A010P
元件分類: 微控制器/微處理器
英文描述: 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53
封裝: DIE-53
文件頁數(shù): 16/159頁
文件大?。?/td> 1200K
代理商: S1C63158D0A010P
104
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Integer Multiplier)
4.12 Integer Multiplier
4.12.1 Configuration of integer multiplier
The S1C63808 has a built-in unsigned-integer multiplier. This multiplier performs 8 bits
× 8 bits of
multiplication or 16 bits
÷ 8 bits of division and returns the results and three flag states.
Figure 4.12.1.1 shows the configuration of the integer multiplier.
Flag
(NF/VF/ZF)
Destination register
High-order byte (DRH)
Low-order byte (DRL)
Data bus
Operation
control
(CALMD)
Source register
(SR)
Temporary
register B
Temporary
register A
Adder
Fig. 4.12.1.1 Configuration of the integer multiplier
4.12.2 Multiplication mode
To perform a multiplication, set the multiplier to the source register (SR) and the multiplicand to the low-
order 8 bits (DRL) of the destination register, then write "0" to the calculation mode selection register
(CALMD). The multiplication takes 10 CPU clock cycles from writing "0" to CALMD until the 16-bit
product is loaded into the destination register (DRH and DRL). At the same time the result is loaded, the
operation flags (NF, VF and ZF) are updated.
The following shows the conditions that change the operation flag states and examples of multiplication.
N flag:
Set when the MSB of DRH is "1" and reset when it is "0".
V flag:
Always reset after a multiplication.
Z flag:
Set when the 16-bit value in DRH/DRL is 0000H and reset when it is not 0000H.
<Examples of multiplication>
DRL (multiplicand)
SR (multiplier) DRH/DRL (product) NF
VF
ZF
00H
64H
0000H
0
1
64H
58H
2260H
0
C8H
58H
44C0H
0
C8H
A5H
80E8H
1
0
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