參數(shù)資料
型號： S1C63158D0A010P
元件分類： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53
封裝： DIE-53
文件頁數(shù)： 144/159頁
文件大?。?/td> 1200K
代理商： S1C63158D0A010P
S1C63808 TECHNICAL MANUAL
EPSON
77
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
In addition, RXTRGx can be read as a status bit. In either clock synchronous mode or asynchronous
mode, when RXTRGx is set to "1", it indicates receiving operation and when set to "0", it indicates that
receiving has stopped.
For details on timing, see the timing chart which gives the timing for each mode.
When you do not receive, set RXENx to "0" to disable receiving.
4.10.6 Operation of clock synchronous transfer
Clock synchronous transfer involves the transfer of 8-bit data by synchronizing it to eight clocks. The
same synchronous clock is used by both the transmitting and receiving sides.
When the serial interface is used in the master mode, the clock signal selected using SCSx0 and SCSx1 is
further divided by 1/16 and employed as the synchronous clock. This signal is then sent via the SCLKx
terminal to the slave side (external serial I/O device).
When used in the slave mode, the clock input to the SCLKx terminal from the master side (external serial
input/output device) is used as the synchronous clock.
In the clock synchronous mode, since one clock line (SCLKx) is shared for both transmitting and receiv-
ing, transmitting and receiving cannot be performed simultaneously. (Half duplex only is possible in
clock synchronous mode.)
The transfer data length is fixed at 8 bits. Data can be switched using a register whether it is transmitted/
received from LSB (bit 0) or MSB (bit 7).
SCLKx
(positive)
Data
D0 D1 D2 D3 D4 D5 D6 D7
LSB
MSB
Data
D0 D1 D2 D3 D4 D5 D6 D7
LSB
MSB
LSB first
SCLKx
(negative)
SCLKx
(positive)
Data
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
MSB first
SCLKx
(negative)
Data
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
Fig. 4.10.6.1 Transfer data configuration using clock synchronous mode
Below is a description of initialization when performing clock synchronous transfer, transmit-receive
control procedures and operations.
With respect to serial interface interrupt, see "4.10.8 Interrupt function".
Initialization of serial interface
When performing clock synchronous transfer, the following initial settings must be made.
(1) Setting of transmitting/receiving disable
To set the serial interface into a status in which both transmitting and receiving are disabled, "0"
must be written to both the transmit enable register TXENx and the receive enable register RXENx.
Fix these two registers to a disable status until data transfer actually begins.
(2) Port selection
Because serial interface input/output ports SINx, SOUTx, SCLKx and SRDYx are set as I/O port
terminals P10–P13 and P20–P23 at initial reset, "1" must be written to the serial interface enable
register ESIFx in order to set these terminals for serial interface use.
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