參數(shù)資料
型號： RTL8305SB
英文描述： RTL8305SB
中文描述： RTL8305SB
文件頁數(shù)： 40/66頁
文件大?。?/td> 963K
代理商： RTL8305SB
RTL8305SB
2002/04/09
40
Rev.1.0
7.2.8 100Base-FX Transmit Function
In 100Base-FX transmit, di-bits of TXD are processed as 100Base-TX except without scrambler before NRZI stage. Instead of
converting to MLT-3 signals as in 100Base-TX, serial data stream is driven out as NRZI PECL signals, which enter the fiber
transceiver in differential-pairs form. The fiber transceiver should be available working in a 3.3V environment. Refer to fiber
application section.
Parameter
PECL Input High Voltage
PECL Input Low Voltage
PECL Output High Voltage
PECL Output Low Voltage
Symbol Min
Vih
Vil
Voh
Vol
PECL DC characteristics
Max
Vdd-0.88
Vdd-1.47
Vdd-1.62
Unit
V
V
V
V
Vdd-1.16
Vdd-1.81
Vdd-1.02
7.2.9 100Base-FX Receive Function
Signals are received through PECL receiver inputs from fiber transceiver, and directly passed to clock recovery circuit for
data/clock recovery. Scrambler/de-scrambler is bypassed in 100Base-FX.
7.2.10 100Base-FX Far-End-Fault-Indication (FEFI)
MII Reg.1.4 (Remote Fault) is the FEFI bit for ports when 100FX is enabled, which indicates that a FEFI has been detected.
FEFI is an alternative in-band signaling which is composed of 84 consecutive ‘1’ followed by one ‘0’. From the view of the
RTL8305SB, when this pattern has been detected three times, Reg.1.4 is set, which means the transmit path (Remote side’s
receive path) has problems. On the other hand, to send FEFI stream pattern, 1 condition need to be satisfied. The incoming
signal failed in causing link OK will force the RTL8305SB to start sending this pattern, which in turn causes the remote side
detecting Far-End-Fault. This means that the receive path has a problem from the view of the RTL8305SB. The FEFI
mechanism is used only in 100Base-FX.
7.2.11 Reduced Fiber Interface
The RTL8305SB ignores the underlying SD signal of the fiber transceiver to complete link detection and connection. This is
achieved by monitoring RD signals from the fiber transceiver and checking if any link integrity events are met. This
significantly reduces pin-count, especially for high-port PHY devices. This is a Realtek patent-pending technology and
available only with Realtek product solutions.
7.2.12 Power Saving Mode
The RTL8305SB implements power saving mode on per port base. A port automatically enters power saving mode 10 seconds
after the cable is disconnected from it. Once a port enters power saving mode, it transmits normal link pulses only on its
TXOP/TXON pins and continues to monitor the RXIP/RXIN pins to detect any incoming signals, which might be the
100Base-TX MLT-3 idle pattern, 10Base-T link pulses or Auto-Negotiation’s FLP (fast link pulses). After it detects any incoming
signals, it wakes up from the power saving mode and operates in the normal mode according to the result of connection.
7.2.13 Reg0.11 Power Down Mode
The RTL8305SB implements power down mode on a per port basis. Setting MII Reg.0.11 forces the corresponding port
of the RTL8305SB to enter power down mode, which disables all transmit/receive functions, except SMI (MDC/MDIO
management interface).
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