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參數(shù)資料
| 型號(hào)： | RTL8305SB |
| 英文描述： | RTL8305SB |
| 中文描述： | RTL8305SB |
| 文件頁(yè)數(shù)： | 11/66頁(yè) |
| 文件大?。?/td> | 963K |
| 代理商： | RTL8305SB |
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RTL8305SB
2002/04/09
11
Rev.1.0
P4DUPSTA/
P4FULL
48
I
Port4 Duplex Status:
Port4 initial configuration pin for Duplex upon
reset for PHY of UTP or FX mode and Duplex Status for MAC of other
mode in real time after reset.
1: Full duplex
0: Half duplex
When P4MODE[1:0]=11 (UTP/MAC mode MII), this pin provides the
initial duplex configuration for the PHY part upon reset (UTP) then
determines the duplex status of MAC mode MII in real time after reset.
The duplex status of the PHY part (UTP) is provided by the internal
PHY in real time after reset.
When P4MODE[1:0]=10 (100Base-FX mode), this pin provides the
initial register configuration of duplex for PHY part upon reset (FX).
The duplex status of the PHY part (FX) is provided by the internal PHY
in real time after reset.
When P4MODE[1:0]=01 (PHY mode MII), this pin determines the
duplex status of Port4 in real time after reset.
When P4MODE[1:0]=00 (PHY mode SNI), this pin determines the
duplex status of Port4 in real time after reset.
8305SB = P4DUPSTA/P4FULL, 8305S = P4DUPSTA#.
In order to provide Full duplex as the default value for the PHY, this pin
is changed as high active.
In 100Base-Fx/ MAC mode MII/ PHY mode MII/ PHY mode SNI, the
configuration of this pin after reset will not set the link status of the
internal register. The link status depends on the external PHY or MAC.
1
Cont…
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