
RTL8801
Preliminary
RTL8801 PHY/IEEE 1394A
3 port 100/200/400 Mb/s Cable Transceiver/Arbiter Chip
1999/3
1
1. Features
Fully support provisions of IEEE1394-1995
for High- Performance Serial Bus and the
P1394a draft 2.0 standard
Provides three fully compliant cables ports at
100/200/400 Mbits/s and available with one,
two or three ports
Fully compliant with Open HCI requirements
Full P1394a additional function support
Support optional 1394 Annex J electrical
isolation barrier at PHY-link interface
Support power-down feature to conserve
energy in battery powered applications
Cable power presence monitoring
Separate cable bias (TPBIAS) and driver
termination voltage supply for each port
Encode and decode functions included for
data-strobe bit level encoding
Support LPS/link-on pin for PHY-link
interface
Incoming data resynchronized to local clock
Single
24.576
MHZ
transmit/receive data at 100/200/400 Mbits/s
and LLC clock at 49.152 M
Node power-class information signaling for
system power management
Adaptive equalizer
Easy configured as a repeater
Single 3.3V power supply
64 pin LQFP package
crystal
provide
2. General Description
The RTL8801 provides three-port physical layer(PHY) function in a cable-based IEEE 1394-1995
and IEEE P1394a network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection
status, for initialization and arbitration, and for packet reception and transmission.
Data bits to be transmitted through the cable ports are received from the Link on 2/4/8 data lines
(D0-D8), and are latched internally in the RTL8801 in synchronization with the 49.152 MHZ
system clock these bits are combined serially, encoded, and transmitted at 98.304 , 196.608 or
393.216Mbps as the outbound data-strobe information stream. During transmission, the encoded
data transmitted differential on the TPB cable pair(s), and the encoded strobe information is