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參數(shù)資料
| 型號(hào)： | RTL8801 |
| 英文描述： | Specifications |
| 中文描述： | 規(guī)格 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 318K |
| 代理商： | RTL8801 |
RTL8801
Preliminary
1999/3
7
6. Functional Description
The operation of the cable PHY can best be understood with reference to the 5.0 block diagram
show before.
The main controller of the cable PHY is the block labeled “” arbitration and control state machine
logic” which responds to arbitration requests from the link layer and changes in the state of attached
ports. It provides the management and timing signals for transmitting, receiving, and repeating
packets. It also provides the bus reset and configuration . The cable environment supports the
immediate, fair, isochronous, and cycle_master arbitration classes, where the cycle_master class is
only available at the root node as described in IEEE1394 stnadard.
Cable arbitration has two parts: a three-phase initialization process (bus reset, tree identify, and
self-identify), and a normal operation phase. Each of these four phases is described using a state
machine, The state machine and the list of actions and conditions are the normative part of IEEE
1394 standard.
The“receive data decoder/retimer” block decodes the data-strobe signal and retimes the received
data to a local fixed-frequency clock provided by the local clock. Since the clocks of receiving and
transmitting nodes can be up to 100 ppm different from the nominal, the data resynch function has
to be able to compensate for a difference of 200 ppm over the maximum packet length of 84.31 us
(1024 byte isochronous packet at 98.304 Mbit/s). Data reception for the cable environment physical
layer has three major functions: decoding the data-strobe signal to recover a clock, synchronizing
the data to a local clock for use by the link layer, repeating the synchronized data out all other
connected ports.
The “”transmit data encoder” block provides a common interface to the link layer for both packet
data and arbitration signal (gaps and bus reset indicators). Data transmission is a straightforward
function: the data bits are sent to the attached peer PHY along with the appropriately encoded
strobe signal using the timing provided by the PHY transmit clock. If connected port cannot accept
data at the requested speed, then no data is send (leaving the drivers in the “01” data prefix
condition).
The “”link interface” block provides a scalable, cost-effective method to connect one serial bus link
chip to one serial bus PHY chip. The width of the data bus scales with the highest speed both chips
can support, using two pins per 100 Mbit/s. The clock rate of the signals at this interface remains
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