參數(shù)資料
型號(hào)： RTL8801
英文描述： Specifications
中文描述： 規(guī)格
文件頁(yè)數(shù)： 8/19頁(yè)
文件大?。?/td> 318K
代理商： RTL8801
RTL8801
Preliminary
1999/3
8
constant, independent of speed, to support galvanic isolation for implementations where it is
desirable. The PHY has control over the bidirectional pins. The link only drives these pins when
control is transferred to it by the PHY. The link performs all unsolicited activity through a
dedicated request pin. The possible actions that may occur on the interface are categorized as
transmit, receive, status, and request.
7. Internal Register Configuration
There are 16 accessible internal registers in the PHY. The configuration of the Register at
addresses 0h to7h is fixed. The register 8h to Fh are an index register window whose contents
change based upon the Page_Slect and Port_Select field in Register 7h.
7.1 PHY register field map for the cable environment
address
0000b
0001b
0010b
0011b
0100b
0
1
2
Physical_ID
3
4
5
6
R
7
PS
RHB
IBR
Gap_count
Total_ports(0011b)
Delay(0000b)
Extended(111b)
Max_speed(010b)
Link_
active
der
Resume_
int
reserved
reserved
Jitter(000b)
Conten
Pwr_class
0101b
ISBR
Loop
Pwr_fail Time
out
Port_event Enab_
accel
Enab_
multi
0110b
0111b
1000b
……..
…….
1111b
Reserved
reserved
Register0(page_select)
Page_select
Port_select
Register7(page_select)
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