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參數(shù)資料
| 型號(hào)： | RTL8801 |
| 英文描述： | Specifications |
| 中文描述： | 規(guī)格 |
| 文件頁(yè)數(shù)： | 4/19頁(yè) |
| 文件大?。?/td> | 318K |
| 代理商： | RTL8801 |
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RTL8801
Preliminary
1999/3
4
4. Pin Descriptions
Symbol
C/LKON
Type
I/O
Pin(s) No.
18
Description
(input) Bus manager capable. When set as input, C/LKON specifies in
the Self-ID packet that the node is bus manager capable.
(output) Link on. When set as an output, C/LKON indicates the
reception of a link-on packet by asserting a 6.114 MHZ square wave
signal.
CNA is asserted high when none of the PHY ports are connected to
another active port. This circuit remains active during the power down
mode.
Cable power status. CPS is normally connected to the cable power
through a 400-Kohm resistor. This circuit drivers an internal
comparator that detects the presence of cable power.
Link power status. LPS is connected to either the VDD supplying the
LINK or to a pulsed output that is active when the LINK is powered
for the purpose of monitoring the LINK power status.
Link request. LREQ is an input from the LINK that requests the PHY
to perform some service.
Link interface isolation input. This pin controls the operation of output
differentiation logic on the CTLn and Dn pin. If an optional isolation
barrier of the type described in Annex J of IEEE 1394-1995 is
implement between the PHY and LLC. This pin should be tied low to
enable the internal differentiation logic.
Control I/O. the CTLn pins are bi-directional communications control
signals between the PHY and LLC.
Data I/O. The D terminals are bi-directional and pass data between the
PHY and LLC.
System clock. SYSCLK provides a 49.152 MHZ clock signal, which is
synchronized with the data transfers to the LLC.
Port1, cable pair A. TPA1 is the port A connection to the twisted-pair
cable .Board traces from each pair of positive and negative differential
signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector
Port2, cable pair A. TPA2 is the port A connection to the twisted-pair
cable .Board traces from each pair of positive and negative differential
signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector
Port3, cable pair A. TPA3 is the port A connection to the twisted-pair
cable .Board traces from each pair of positive and negative differential
signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector
Port1, cable pair B. TPB1 is the port B connection to the twisted-pair
cable .Board traces from each pair of positive and negative differential
signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector
Port2, cable pair B. TPB2 is the port B connection to the twisted-pair
cable .Board traces from each pair of positive and negative differential
signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector
Port3, cable pair B. TPB3 is the port B connection to the twisted-pair
cable .Board traces from each pair of positive and negative differential
signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector
CNA
O
15
CPS
I
24
LPS
I
16
LREQ
I
1
ISO\
I
23
CTL0
CTL1
D0-D7
I/O
3,4
I/O
5, 6, 8, 9, 10,
11, 12, 13
63
SYSCLK
O
TPA1+
TPA1-
I/O
36, 35
TPA2+
TPA2-
I/O
41, 40
TPA3+
TPA3-
I/O
47, 46
TPB1+
TPB1-
I/O
34, 33
TPB2+
TPB2-
I/O
39, 38
TPB3+
TPB3-
I/O
45, 44
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