參數(shù)資料
型號: RTL8305SB
英文描述: RTL8305SB
中文描述: RTL8305SB
文件頁數(shù): 2/66頁
文件大小: 963K
代理商: RTL8305SB
1. Features
RTL8305SB
2002/04/09
2
Rev.1.0
5-port integrated switch controller with memory and
transceiver for 10Base-T and 100Base-TX with
5-port 10/100M UTP or
4-port 10/100M UTP + 1-port MII/SNI
Supports PHY mode MII /SNI for router applications
and MAC mode MII for HomePNA or VDSL solutions
All ports support 100Base-FX with optional flow
control enable/disable and full/half duplex setting
Non-blocking wire-speed reception and transmission
and non-head-of-line-blocking forwarding
Fully compliant with IEEE 802.3/802.3u
auto-negotiation function
Built-in high efficiency SRAM for packet buffer and
1K entry look-up table, and 16 entry CAM
Supports broadcast storm filtering function
Supports IEEE802.3x full duplex flow control and
back pressure half duplex flow control
Supports SMI (Serial Management Interface:
MDC/MDIO) for programming and diagnostics
Supports loop detection function with one LED to
indicate the existence of loop
Supports loopback function for diagnosis
Flexible 802.1Q Port based VLAN. Up to 5 VLAN
Supports 802.1Q tag VLAN function
Supports ARP VLAN for broadcast packets
Supports Leaky VLAN for unicast packets
Supports QoS function on each port:
QoS based on: (1) Port-based (2) VLAN tag
(3) TCP/IP header’s TOS/DS
Supports two level priority queues
Weighted round robin service
Supports VLAN priority tag Insert/Remove function
Optional 1536 or 1552 byte maximum packet length
Supports reserved control frames (DID=
0180C2000003~0180C200000F) filtering function
Flexible LED indicators for link, activity, speed,
full/half duplex and collision
LEDs blink upon reset for LED diagnostics
Supports two Power Reduction methods:
Power saving mode by cable detection
Power down mode (by PHY register 0.11)
Robust baseline wander correction for improved
100BASE-TX performance
Optional Crossover Detection and Auto Correction
function
Physical layer port Polarity Detection and Correction
function
Optional
EEPROM interface for configuration
25MHz crystal or OSC input. Single 3.3V power
system like by translating of an external transistor
0.25 μm, CMOS technology, 3.3V/2.5V with 3.3V
input tolerant, 128 pin PQFP package
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