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參數(shù)資料
| 型號： | RTL8305SB |
| 英文描述： | RTL8305SB |
| 中文描述： | RTL8305SB |
| 文件頁數(shù)： | 22/66頁 |
| 文件大小： | 963K |
| 代理商： | RTL8305SB |
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RTL8305SB
2002/04/09
22
Rev.1.0
6.1 PHY0 to 4: PHY Register of Each Port
6.1.1 Register0: Control Register
Reg.bit
0.15
0.14
Name
Reset
Loopback
(digital loopback)
Description
Reset:
1: PHY reset. This bit is self-clearing.
Enable Loopback:
This pin enables loopback from the MII TXD
to the MII RXD and ignores all the activities on the cable media.
Mode
RW/SC
RW
Default
0
0
1: Enable loopback
0: Normal operation
This function is usable only when this PHY is 10Based-T full
duplex or 100Base-T full duplex.
The packet is forwarded from other PHY (could be 10Based-T,
or 100TX, or 100FX, both full and half duplex) by switch core
and will loopback to the switch core. It could be forwarded to
the other port or dropped depending on the destination and
source MAC address of the packet.
Speed Select:
0.13
Spd_Sel
1: 100Mbps
0: 10Mbps
When Nway is enabled, this bit reflects the result of
auto-negotiation. (Read only)
When Nway is disabled, this bit can be set through SMI.
(Read/Write)
When 100FX mode is enabled, this bit =1. (Read only)
1: Enable auto-negotiation process
0: Disable auto-negotiation process
RW
From pin
0.12
Auto Negotiation
Enable
This bit can be set through SMI.(Read/Write)
When 100FX mode is enabled, this bit =0.(Read only)
100FX should be force mode. In order to avoid errors, the
RTL8305SB will ignore the action to this bit when writing
Reg0.12 as 1 in 100FX mode.
1: Power down. All functions will be disabled except SMI
function and internal TXC to MAC.
0: Normal operation.
1: Electrically isolate the PHY from internal MII. The PHY is
still able to response to MDC/MDIO.
0: Normal operation
1: Restart Auto-Negotiation process.
0: Normal operation.
Duplex mode:
1: Full duplex operation
0: Half duplex operation
When Nway is enabled (Reg0.12=1), this bit reflects the result
of auto-negotiation. (Read only)
RW
From pin
0.11
Power Down
RW
0
0.10
Isolate
RW
0
0.9
Restart Auto
Negotiation
Duplex Mode
RW/SC
0
0.8
When Nway is disabled (Reg0.12=0, force mode of UTP or
100FX), this bit can be set through SMI*. (Read/Write)
100FX should be force mode. In order to avoid errors, the
RTL8305SB will ignore the action to this bit when writing
Reg0.12 as 1 in 100FX mode.
RW
From pin
0.[7:0]
Reserved
RO
0
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